Semiconductor devices having buried contact structures

Patent metadata

Field	Value
Publication number	US-9812539-B2
Application number	US-201514962003-A
Country	US
Kind code	B2
Filing date	Dec 8, 2015
Priority date	Dec 17, 2014
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

Semiconductor devices are provided including a substrate defining a gate trench. A buried gate structure is provided in the gate trench and at least fills the gate trench. The buried gate structure includes a gate insulation layer pattern, a gate electrode and a capping layer pattern. First and second impurity regions are provided at portions of the substrate adjacent to the buried gate structure, respectively. At least a portion of each of the first and second impurity regions face a sidewall of the buried gate structure. First and second buried contact structures are provided on the first and second impurity regions, respectively. Each of the first and second buried contact structures includes a metal silicide pattern and a metal pattern, and at least a portion of each of the first and second buried contact structures face to a sidewall of the buried gate structure.

First claim

What is claimed is:

1. A semiconductor device, comprising: a substrate defining a gate trench therein;
a buried gate structure in the gate trench and at least filling the gate trench to a top portion thereof, the buried gate structure including a gate insulation layer pattern, a gate electrode and a capping layer pattern;
first and second impurity regions in the substrate on opposite sides of the buried gate structure, at least a portion of each of the first and second impurity regions facing a sidewall of the buried gate structure; and
first and second buried contact structures on the first and second impurity regions, respectively, each of the first and second buried contact structures including a metal silicide pattern and a metal pattern, and at least a portion of each of the first and second buried contact structures facing a sidewall of the buried gate structure; and
an isolation layer on the substrate, wherein a top surface of the isolation layer is substantially coplanar with top surfaces of the first and second buried contact structures,
wherein top surfaces of the first and second buried contact structures are substantially coplanar with that of the buried gate structure;
wherein bottom surfaces of the first and second impurity regions are substantially coplanar with a bottom surface of the gate electrode of the buried gate structure; and

wherein bottom surfaces of the first and second impurity regions are flat.

2. The semiconductor device of claim 1 , wherein the buried gate structure protrudes from a top portion of the gate trench.

3. The semiconductor device of claim 1 , wherein top surfaces of the first and second impurity regions are lower than top portions of the gate electrode.

4. The semiconductor device of claim 1 , wherein bottoms of the first and second impurity regions are lower than a central portion of the gate electrode corresponding to about ½ of a height of the gate electrode.

5. The semiconductor device of claim 1 , wherein the metal silicide pattern directly contacts each of the first and second impurity regions.

6. The semiconductor device of claim 1 , wherein a bottom of the metal silicide pattern is lower than a top surface of the gate electrode.

7. The semiconductor device of claim 1 , wherein the metal silicide pattern includes at least one selected from the group consisting of cobalt silicide, nickel silicide, titanium silicide, tantalum silicide, molybdenum silicide, and tungsten silicide.

8. A semiconductor device, comprising: a substrate defining a gate trench therein;
a buried gate structure in the gate trench and at least filling the gate trench to a top portion thereof, the buried gate structure including a gate insulation layer pattern, a gate electrode and a capping layer pattern;
first and second impurity regions in the substrate on opposite sides of the buried gate structure, at least a portion of each of the first and second impurity regions facing a sidewall of the buried gate structure;
first and second buried contact structures on the first and second impurity regions, respectively, each of the first and second buried contact structures including a metal silicide pattern and a metal pattern, and at least a portion of each of the first and second buried contact structures facing a sidewall of the buried gate structure; and
a first contact plug on the first buried contact structure; a second contact plug on the second buried contact structure; a bit line electrically connected to the first contact plug; and a capacitor on the second contact plug*
wherein top surfaces of the first and second buried contact structures are substantially coplanar with that of the buried gate structure;
wherein bottom surfaces of the first and second impurity regions are substantially coplanar with a bottom surface of the gate electrode of the buried gate structure; and
wherein bottom surfaces of the first and second impurity regions are flat.

9. The semiconductor device of claim 1 , further comprising:
a source line on the first buried contact structure;
a contact plug on the second buried contact structure;
a variable resistance structure electrically connected to the contact plug; and
a bit line on the variable resistance structure.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Yong-Jun
• Kim Sung-In
• Song Jung-Woo
• Kahng Jae-Rok
• Kim Dae-Won

Classifications

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/021

  of interconnections within wafers or substrates · CPC title

• H01L27/10876

  Electricity · mapped topic

• H01L27/10855

  Electricity · mapped topic