Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices

US9812415B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9812415-B2
Application numberUS-201414506423-A
CountryUS
Kind codeB2
Filing dateOct 3, 2014
Priority dateMar 13, 2007
Publication dateNov 7, 2017
Grant dateNov 7, 2017

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  1. Title

    What the patent document calls the invention.

  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed. In one embodiment, a method for forming a microelectronic device includes attaching a microelectronic die to a support member by forming an attachment feature on at least one of a back side of the microelectronic die and the support member. The attachment feature includes a volume of solder material. The method also includes contacting the attachment feature with the other of the microelectronic die and the support member, and reflowing the solder material to join the back side of the die and the support member via the attachment feature. In several embodiments, the attachment feature is not electrically connected to internal active structures of the die.

First claim

Opening claim text (preview).

We claim: 1. A method for mounting a semiconductor device to a circuit board, the method comprising: depositing a plurality of pre-formed solder balls on at least a portion of a device attach region of the circuit board; juxtaposing a back side of the semiconductor device and the pre-formed solder balls; forming a generally rigid connection between the back side of the semiconductor device and the circuit board by contacting the pre-formed solder balls with a conductive layer and reflowing the pre-formed solder balls and conductive layer to form a single, unitary connection structure, wherein the conductive layer covers all of the back side of the semiconductor device: and forming a plurality of wire bonds between terminals at a front side of the semiconductor device and corresponding contacts on the circuit board after forming the generally rigid connection between the semiconductor device and the circuit board. 2. The method of claim 1 wherein forming a generally rigid connection between the back side of the semiconductor device and the circuit board comprises attaching the semiconductor device to the circuit board in a chip-on-board (COB) configuration. 3. The method of claim 1 wherein depositing a plurality of pre-formed solder balls on at least a portion of a device attach area comprises depositing solder balls composed of at least one of a SnAgCu, SnAg, and SnAu solder material. 4. The method of claim 1 , further comprising depositing a non-conductive fill material in one or more interstitial spaces between the semiconductor device and the circuit board after forming the generally rigid connection. 5. The method of claim 1 , further comprising encapsulating the semiconductor device, the wire bonds, and at least a portion of the circuit board after forming the wire bonds. 6. The method of claim 1 wherein depositing a plurality of pre-formed solder balls on at least a portion of a device attach area comprises depositing solder balls composed of lead-free solder material. 7. The method of claim 1 , further comprising depositing a conductive layer on the back side of the semiconductor device, the conductive layer having a plurality of conductive pads arranged in a pattern corresponding at least in part to the arrangement of solder balls. 8. The method of claim 1 wherein forming a generally rigid connection between the back side of the semiconductor device and the circuit board comprises forming a connection structure that does not transmit signals between the semiconductor device and the circuit board.

Assignees

Inventors

Classifications

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • on active surfaces of flip-chip devices, e.g. underfills · CPC title

  • Encapsulations, e.g. protective coatings · CPC title

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Frequently asked questions

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What does patent US9812415B2 cover?
Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed. In one embodiment, a method for forming a microelectronic device includes attaching a microelectronic die to a support member by forming an attachment feature on at least one of a back side of the microelectronic die and the support member. The attachment feature includes a volume of s…
Who is the assignee on this patent?
Micron Technology Inc
What technology area does this patent fall under?
Primary CPC classification H10W74/01. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 07 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).