Semiconductor substrate, semiconductor module and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9812387-B2
Application number	US-201615364143-A
Country	US
Kind code	B2
Filing date	Nov 29, 2016
Priority date	Jul 13, 2015
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

A semiconductor substrate includes: 1) a first dielectric structure having a first surface and a second surface opposite the first surface; 2) a second dielectric structure having a third surface and a fourth surface opposite the third surface, wherein the fourth surface faces the first surface, the second dielectric structure defining a through hole extending from the third surface to the fourth surface, wherein a cavity is defined by the through hole and the first dielectric structure; 3) a first patterned conductive layer, disposed on the first surface of the first dielectric structure; and 4) a second patterned conductive layer, disposed on the second surface of the first dielectric structure and including at least one conductive trace. The first dielectric structure defines at least one opening to expose a portion of the second patterned conductive layer.

First claim

What is claimed is:

1. A semiconductor substrate, comprising:
a first dielectric structure having a first surface and a second surface opposite the first surface;
a second dielectric structure having a third surface and a fourth surface opposite the third surface, wherein the fourth surface faces the first surface, the second dielectric structure defining a through hole extending from the third surface to the fourth surface, wherein a cavity is defined by the through hole and the first dielectric structure;
a first patterned conductive layer, disposed on the first surface of the first dielectric structure; and
a second patterned conductive layer, disposed on and contacting the second surface of the first dielectric structure and including at least one conductive trace;
wherein the first dielectric structure defines at least one opening to expose a portion of the second patterned conductive layer.

2. The semiconductor substrate of claim 1 , wherein the first patterned conductive layer is embedded in the second dielectric structure.

3. The semiconductor substrate of claim 1 , further comprising at least one electrical contact disposed on the second patterned conductive layer and being exposed from the opening.

4. The semiconductor substrate of claim 3 , wherein the at least one electrical contact is a plurality of electrical contacts and the at least one opening is a plurality of openings, wherein each of the openings corresponds to a respective one of the electrical contacts.

5. The semiconductor substrate of claim 4 , wherein the conductive trace is positioned between the openings.

6. The semiconductor substrate of claim 1 , wherein the opening is recessed from the first surface of the first dielectric structure.

7. The semiconductor substrate of claim 1 , wherein the at least one opening is a single opening, and a periphery of the single opening corresponds to a periphery of the cavity such that a surface of the first dielectric structure at a bottom of the single opening is a bottom surface of the cavity.

8. The semiconductor substrate of claim 1 , wherein the second dielectric structure is a build-up layer.

9. The semiconductor substrate of claim 1 , further comprising:
at least one first via embedded in the first dielectric structure and connecting the first patterned conductive layer and the second patterned conductive layer, wherein the first via includes an upper portion and a lower portion, and a width of the upper portion of the first via is less than a width of the lower portion of the first via;
a third patterned conductive layer on the third surface; and
at least one second via embedded in the second dielectric structure and connecting the first patterned conductive layer and the third patterned conductive layer, wherein the second via includes an upper portion and a lower portion, and a width of the upper portion of the second via is greater than a width of the lower portion of the second via.

10. The semiconductor substrate of claim 1 , wherein a material of the first dielectric structure is different from a material of the second dielectric structure.

11. The semiconductor substrate of claim 9 , further comprising:
a positioning structure embedded in the first dielectric structure and exposed from the second surface of the first dielectric structure, the positioning structure disposed around the at least one first via.

12. The semiconductor substrate of claim 1 , further comprising:
a positioning structure embedded in the second dielectric structure and exposed in the through hole, and the positioning structure is disposed around the through hole.

13. A semiconductor module, comprising:
a semiconductor substrate, comprising
a first dielectric structure, having a first surface and a second surface opposite the first surface;
a second dielectric structure, having a third surface and a fourth surface opposite the third surface, wherein the fourth surface faces the first surface, the second dielectric structure defining a through hole extending from the third surface to the fourth surface, wherein a cavity is defined by the through hole and the first dielectric structure;
a first patterned conductive layer, disposed on the first surface of the first dielectric structure; and
a second patterned conductive layer, disposed on the second surface of the first dielectric structure and including at least one conductive trace; and

an electrical component disposed in the cavity and electrically connected to the second patterned conductive layer, wherein the electrical component includes at least two electrodes, and the conductive trace is positioned between the electrodes of the electrical component.

14. The semiconductor module of claim 13 , wherein the electrical component is a passive component.

15. The semiconductor module of claim 13 , further comprising a plurality of electrical contacts embedded in the first dielectric structure, wherein the electrical contacts are disposed on the second patterned conductive layer and are exposed from the first dielectric structure, and the electrodes of the electrical component are connected to the electrical contacts.

16. The semiconductor module of claim 15 , wherein the first dielectric structure defines at least one opening on the first surface to expose the electrical contacts within the cavity.

17. The semiconductor module of claim 16 , wherein the at least one opening is a plurality of openings, and each of the openings corresponds to a respective one of the electrical contacts.

18. The semiconductor module of claim 16 , wherein the at least one opening is a single opening, and a periphery of the single opening corresponds to a periphery of the cavity.

19. A semiconductor module, comprising:
a semiconductor substrate, comprising
a first dielectric structure, having a first surface and a second surface opposite the first surface;
a second dielectric structure, having a third surface and a fourth surface opposite the third surface, wherein the fourth surface is adjacent to the first surface, the second dielectric structure defining a through hole extending from the third surface to the fourth surface, wherein a cavity is defined by the through hole and the first dielectric structure;
a first patterned conductive layer, disposed on the first surface of the first dielectric structure; and
a second patterned conductive layer, disposed on and contacting the second surface of the first dielectric structure; and

an electrical component disposed in the cavity and electrically connected to the second patterned conductive layer.

20. The semiconductor module of claim 19 , wherein the electrical component is a passive component.

21. The semiconductor module of claim 19 , further comprising at least one electrical contact embedded in the first dielectric structure, wherein the electrical component includes at least one electrode, the electrical contact is electrically connected to the second patterned conductive layer and is exposed from the first dielectric structure, and the electrode of the electrical component is connected to the electrical contact.

22. The semiconductor module of claim 21 , wherein the first dielectric structure defines at least one opening on the first surface to expose the electrical contact within the cavity.

23. The semiconductor module of claim 22 , wherein the at least one electrical contact is a plurality of electrical contacts and the at least one opening is a plural

Assignees

• Advanced Semiconductor Eng

Inventors

• Tsai Li-Chuan
• Lee Chih-Cheng

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W70/682

  comprising holes having chips therein · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/635

  Through-vias · CPC title