Automatic test-pattern generation for memory-shadow-logic testing

Patent metadata

Field	Value
Publication number	US-9812219-B2
Application number	US-201514640601-A
Country	US
Kind code	B2
Filing date	Mar 6, 2015
Priority date	Jul 1, 2011
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

An embodiment of a method for automated test pattern generation (ATPG), a system for ATPG, and a memory configured for ATPG. For example, an embodiment of a memory includes a first test memory cell, a data-storage memory cell, and a test circuit configured to enable the test cell and to disable the data-storage cell during a test mode.

First claim

The invention claimed is:

1. A method for automated test pattern generation (ATPG), the method comprising:
generating a test pattern using respective ATPG memory address locations of a memory coupled to a logic circuit under test, in an ATPG mode of operation;
wherein the generation of the test pattern using the respective ATPG memory address locations produces a voltage differential at inputs to sense amplifiers coupled to the memory that is substantially equal to a voltage differential produced at the inputs to the sense amplifiers by data memory address locations of the memory during a normal mode of operation;
applying the generated test pattern to the logic circuit under test.

2. The method as claimed in claim 1 , wherein the respective ATPG memory address locations comprise the same column in two rows of a column mux=“m” memory, where m≧1.

3. The method as claimed in claim 2 , wherein a memory cell at said column in one of said two row lines is programmed for program value ‘0’ and a memory cell at said column in the other of said two row lines is programmed for program value ‘1’.

4. The method as claimed in claim 3 , wherein selecting between program value ‘0’ and program value ‘1’ is controlled by controlling precharge devices coupled to Bitline True (BLT) and Bitline Bar (BLB) of the memory cell at the column in one of the two row lines and the memory cell at the column in the other of the two row lines.

5. The method as claimed in claim 4 , wherein, where m>1, selecting between program value ‘0’ and program value ‘1’ is further controlled by controlling column mux devices coupled to BLT and BLB of the memory cell at the column in one of the two row lines and the memory cell at the column in the other of the two row lines.

6. The method as claimed in claim 5 , wherein logic levels of the column mux devices are controlled to be opposite to those of the precharge devices.

7. The method as claimed in claim 1 , wherein, when the memory is organized as column mux=“m”, where m>1, the respective ATPG memory address locations comprise different columns in a single row.

8. The method as claimed in claim 7 , wherein memory cell at one of said different columns is programmed for program value ‘0’ and a memory cell at the other column is programmed for program value ‘1’.

9. The method as claimed in claim 8 , wherein selecting between program value ‘0’ and program value ‘1’ is controlled by controlling column mux devices and precharge devices coupled to Bitline True (BLT) and Bitline Bar (BLB) of the memory cell of one of the different columns and the memory cell at the other column.

10. The method as claimed in claim 9 , wherein a selection control of the precharge devices is an invert of a selection control of the columns mux devices.

11. The method as claimed in claim 1 , comprising disabling a row decoder of the memory and using an ATPG world line generator for selecting the ATPG memory address locations.

12. The method as claimed in claim 1 , comprising providing voltage differentials associated with respective ATPG memory address locations to a sense amplifier of the memory for output into the logic under test.

13. A system for automated test pattern generation (ATPG), the system comprising:
means for generating a test pattern using respective ATPG memory address locations of a memory coupled to a logic circuit under test, in an ATPG mode of operation, wherein the generation of the test pattern using the respective ATPG memory address locations produces a voltage differential at inputs to sense amplifiers coupled to the memory that is substantially equal to a voltage differential produced at the inputs to the sense amplifiers by data memory address locations of the memory during a normal mode of operation;
means for applying the generated test pattern to the logic circuit under test.

14. The system as claimed in claim 13 , wherein the respective ATPG memory address locations comprise the same column in two row of a column mux=“m” memory, where m≧1.

15. The system as claimed in claim 14 , wherein a memory cell at said column in one of said two row lines is programmed for program value ‘0’ and a memory cell at said column in the other of said two row lines is programmed for program value ‘1’.

16. The system as claimed in claim 15 , wherein a means for selecting between program value ‘0’ and program value ‘1’ is configured to control precharge devices coupled to Bitline True (BLT) and Bitline Bar (BLB) of the memory cell at the column in one of the two row lines and the memory cell at the column in the other of the two row lines.

17. The system as claimed in claim 16 , wherein, where m>1, the means for selecting between program value ‘0’ and program value ‘1’ is further configured to control column mux devices coupled to BLT and BLB of the memory cell at the column in one of the two row lines and the memory cell at the column in the other of the two row lines.

18. The system as claimed in claim 17 , wherein the means for selecting is configured such that logic levels of the column mux devices are controlled to be opposite to those of the precharge devices.

19. The system as claimed in claim 13 , wherein, when the memory is organized as column mux=“m”, where m>1, the respective ATPG memory address locations comprise different columns in a single row.

20. The system as claimed in claim 19 , wherein a memory cell at one of said different columns is programmed for program value ‘0’ and a memory cell at the other column is programmed for program value ‘1’.

21. The system as claimed in claim 20 , wherein a means for selecting between program value ‘0’ and program value ‘1’ is configured to control column mux devices and precharge devices coupled to Bitline True (BLT) and Bitline Bar (BLB) of the memory at one of the different columns and the memory cell at the other column.

22. The system as claimed in claim 21 , wherein the means for selecting is configured such that a selection control of the precharge devices is an inverse of a selection control of the columns mux devices.

23. The system as claimed in claim 13 , further comprising means for disabling a Rowdecoder of the memory and using an ATPG world line generator for selecting the ATPG memory address locations.

24. The system as claimed in claim 13 , further comprising a sense amplifier of the memory, wherein the sense amplifier is configured to receive voltage differentials associated with respective ATPG memory address locations for output into the logic under test.

Assignees

• St Microelectronics Int Nv

Inventors

• Kohli Nishu

Classifications

• G01R31/318307

  computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging · CPC title

• G11C29/56004 Primary

  Pattern generation · CPC title

• G11C29/00

  Checking stores for correct operation {; Subsequent repair}; Testing stores during standby or offline operation · CPC title

• G11C11/4063

  Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing · CPC title

• G01R31/318371

  Methodologies therefor, e.g. algorithms, procedures · CPC title