Threshold voltage analysis

Patent metadata

Field	Value
Publication number	US-2016358647-A1
Application number	US-201615244424-A
Country	US
Kind code	A1
Filing date	Aug 23, 2016
Priority date	May 23, 2014
Publication date	Dec 8, 2016
Grant date	—

Abstract

Apparatuses and methods for threshold voltage analysis are described. One or more methods for threshold voltage analysis include storing expected state indicators corresponding to a group of memory cells, applying a first sensing voltage to a selected access line to which the group of memory cells is coupled, sensing whether at least one of the memory cells of the group conducts responsive to the first sensing voltage, determining whether a discharge indicator for the at least one of the memory cells has changed responsive to application of the first sensing voltage, and determining that the first sensing voltage is the threshold voltage for a particular program state of the at least one of the memory cells.

First claim

1 - 20 . (canceled)

21 . An apparatus, comprising:
an array of memory cells; control circuitry configured to apply a first sensing voltage to a selected access line to which a group of memory cells is coupled; and sense circuitry configured to sense whether at least one of the memory cells of the group conducts responsive to the first sensing voltage; and wherein the apparatus is configured to: determine whether conduction of the at least one of the memory cells has changed responsive to the first sensing voltage by reference to a stored indicator of conduction for the at least one of the memory cells; and determine whether the first sensing voltage is the threshold voltage for a particular program state of the at least one of the memory cells.

22 . The apparatus of claim 21 , wherein the apparatus is further configured to:
compare stored expected state indicators with the stored indicator of conduction for the at least one of the memory cells to determine whether the first sensing voltage is the threshold voltage for the particular program state of the at least one of the memory cells.

23 . The apparatus of claim 21 , wherein the sense circuitry is further configured to:
sense, using the first sensing voltage, a group of memory cells each programmed to one of a number of target states and coupled to the selected access line.

24 . The apparatus of claim 21 , wherein the first sensing voltage is one of a stored series of sensing voltages to be used to determine threshold voltages corresponding to the group of memory cells.

25 . The apparatus of claim 21 , wherein the first sensing voltage is one of a stored series of sensing voltages to be used subsequently as sensing voltages to sense the group of memory cells.

26 . The apparatus of claim 21 , wherein the group of memory cells comprises a page of memory cells.

27 . The apparatus of claim 21 , wherein the apparatus is further configured to determine which of the memory cells conduct responsive to the first sensing voltage.

28 . The apparatus of claim 21 , wherein the apparatus is further configured to determine an indicator of conduction for each of the memory cells that indicates whether each of the memory cells conducts responsive to the first sensing voltage.

29 . The apparatus of claim 21 , wherein the apparatus is further configured to not change a value of an indicator of conduction at sensing voltages higher than the first sensing voltage.

30 . The apparatus of claim 21 , wherein the apparatus is further configured to determine whether the first sensing voltage is a lowermost sensing voltage of a series of sensing voltages that causes the at least one of the memory cells to conduct.

31 . An apparatus, comprising:
an array of memory cells; control circuitry configured to successively apply a plurality of stored sensing voltages to a selected access line of the array of memory cells; and sense circuitry configured to sense whether each respective memory cell h of a group of memory cells coupled to the selected access line begins to conduct responsive to application of the stored sensing voltages; wherein the apparatus is configured to: store counts to indicate a total number of memory cells of the group that each begin to conduct at a lowermost sensing voltage of the plurality of stored sensing voltages; and analyze stored expected data values in comparison to the stored counts to determine an appropriate sensing voltage.

32 . The apparatus of claim 31 , wherein the apparatus is further configured to:
store expected state indicators to indicate the expected program state of each of a number of preprogrammed memory cells.

33 . The apparatus of claim 31 , wherein the apparatus is further configured to:
store a discharge indicator for each of a number of memory cells that indicates a lowermost voltage, when each begins to conduct, responsive to the plurality of stored sensing voltages.

34 . The apparatus of claim 31 , wherein a controller external to a die is configured to analyze stored expected state indicators in comparison to the stored counts to determine an appropriate sensing threshold voltage between at least a first program state and a second program state.

35 . The apparatus of claim 31 , wherein the apparatus is further configured to:
send the stored counts to a controller for analysis after counts for a page of memory cells are stored.

36 . An apparatus, comprising:
an array of memory cells; control circuitry configured to successively apply a plurality of stored sensing voltages to a selected access line of the array of memory cells; and sense circuitry configured to sense conduction of a group of memory cells coupled to the selected access line responsive to application of the plurality of stored sensing voltages to the selected access line; and wherein the apparatus is configured to: store an indicator for each of a number of memory cells in the group that indicates whether conduction occurs responsive to the application of the plurality of stored sensing voltages; and determine whether conduction of at least one of the memory cells has changed responsive to the application of the plurality of stored sensing voltages by reference to the stored indicator for the at least one of the memory cells.

37 . The apparatus of claim 36 , wherein the apparatus is further configured to:
store the indicator for each of the number of memory cells that indicates when each begins to conduct in the range of stored sensing voltages.

38 . The apparatus of claim 36 , wherein;
the indicator indicates a lowermost voltage by execution of instructions to force the indicator to a value indicative of no conduction if at least one selected memory cell conducts at a lower applied sensing voltage than a currently applied sensing voltage.

39 . The apparatus of claim 36 , wherein the apparatus is further configured to output indicators as bits for a first program state.

40 . The apparatus of claim 36 , wherein the apparatus is further configured to:
form a bit count distribution; and send the bit count distribution to a controller for analysis after an uppermost voltage in the range of stored sensing voltages is applied and the resultant bit count distribution is stored.

Assignees

• Micron Technology Inc

Inventors

• Filipiak William C
• Moschiano Violante

Classifications

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C11/5642 Primary

  Sensing or reading circuits; Data output circuits · CPC title