Display device and driving method thereof

Patent metadata

Field	Value
Publication number	US-9812090-B2
Application number	US-201615044571-A
Country	US
Kind code	B2
Filing date	Feb 16, 2016
Priority date	Jun 10, 2015
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

A display device includes a display unit including a light emitting device, data and gate driver for respectively applying data and gate voltages to the display unit, and a signal controller for transmitting, to the data driver, image data having a clock embedded therein. The data driver recovers a first internal reference clock during a low period of a first frame control signal, using the image data having the clock embedded therein, compares the frequency of the recovered first internal reference clock with the frequency of a previously stored reference clock, when the frequency of the recovered first internal reference clock is within an error range of the frequency of the previously stored reference clock, outputs the recovered first internal reference clock and receives a second frame control signal, and when the second frame control signal corresponds to a CDR unit operating condition, recovers a second internal reference clock.

First claim

What is claimed is:

1. A display device comprising:
a display unit configured to display an image using a light emitting device;
a signal controller configured to transmit an image signal and a control signal, the image signal is embedded with a clock signal;
a data driver comprising a clock data recovery (CDR) circuit that extracts from the image signal a first internal reference clock signal during an inactive period of a first frame control signal;
a memory that stores the frequency of a preset reference clock signal;
a comparator that compares the frequency of the recovered first internal reference clock signal with the frequency of the preset reference clock signal, wherein when the frequency of the recovered first internal reference clock signal is within an error range of the frequency of the preset reference clock signal, outputs the recovered first internal reference clock signal, and receives a second frame control signal, and when the second frame control signal corresponds to a previously set CDR circuit operating condition, recovers a second internal reference clock signal.

2. The display device of claim 1 ,
wherein the data driver includes:
a CDR circuit configured to recover the first internal reference clock signal and the second internal reference clock signal; the memory configured to store the frequency of the preset reference clock signal;
the comparator configured to receive the first internal reference clock signal, compare the frequency of the preset reference clock signal with the frequency of the first internal reference clock signal, and when the frequency of the recovered first internal reference clock signal is within the error range of the frequency of the preset reference clock signal output the recovered first internal reference clock signal; and
a pulse counter configured to receive the second frame control signal, determine whether the second frame control signal corresponds to the previously set CDR circuit operating condition, and when the second frame control signal corresponds to the previously set CDR circuit operating condition, transmit the second frame control signal to the CDR circuit.

3. The display device of claim 2 , wherein, when the frequency of the recovered first internal reference clock signal is out of the error range of the frequency of the preset reference clock signal, the data driver initializes the pulse count, and outputs the recovered first internal reference clock signal.

4. The display device of claim 1 , wherein the data driver determines which number of a sequence of the inactive period the second frame control signal corresponds to and sets a pulse count to the determined number of times, determines whether the pulse count is identical to a previously set CDR circuit operating value, and when the pulse count is identical to the previously set CDR circuit operating value, recovers the second internal reference clock signal during the inactive period of the second frame control signal.

5. The display device of claim 4 , wherein the previously set CDR circuit operating value is 2 N , where N is 0 or a multiple of 2.

6. The display device of claim 1 , wherein, when the pulse count is not identical to the previously set CDR circuit operating value, the data driver omits the recovery of the second internal reference clock signal during the inactive period of the second frame control signal.

7. The display device of claim 1 , wherein the first frame control signal is a start frame control (SFC) signal.

8. The display device of claim 1 , wherein, when the frequency of the recovered first internal reference clock signal is within the error range of the frequency of the preset reference clock signal, the data driver generates a control signal including information that the operation of the CDR circuit is to be stopped during a predetermined period.

9. A method of driving a display device, the method comprising:
receiving a first frame control signal; recovering a first internal reference clock signal during a inactive period of the first frame control signal;
comparing the frequency of the recovered first internal reference clock signal with the frequency of a preset reference clock signal,
wherein when the frequency of the recovered first internal reference clock signal is within an error range of the frequency of the preset reference clock signal, outputting the recovered first internal reference clock signal;
receiving a second frame control signal; and when the second frame control signal corresponds to a previously set CDR circuit operating condition, recovering the second internal reference clock signal.

10. The method of claim 9 , wherein the recovering of the second internal reference clock signal includes:
determining which number of a sequence the inactive period of the second frame control signal corresponds to and setting a pulse count to the determined number of times; determining whether the pulse count is identical to a previously set CDR circuit operating value; and
when the pulse count is identical to the previously set CDR circuit operating value, recovering the second internal reference value during the inactive period of the second frame control signal.

11. The method of claim 10 , further comprising, when the pulse count is not identical to the previously set CDR circuit operating value, omitting the recovery of the second internal reference clock signal during the inactive period of the second frame control signal.

12. The method of claim 10 , further comprising:
when the frequency of the recovered first internal reference clock signal is out of the error range of the frequency of the preset reference clock signal, initializing the pulse count; and
outputting the recovered first internal reference clock signal.

13. The method of claim 10 , wherein the first frame control signal is an SFC signal.

14. The method of claim 10 , wherein the previously set CDR circuit operating value is 2 n , where N is 0 or a multiple of 2.

15. The method of claim 9 , further comprising, when the frequency of the recovered first internal reference clock signal is within the error range of the frequency of the preset reference clock signal, generating a control signal including information that the operation of the CDR circuit is to be stopped during a predetermined period.

16. A display device comprising:
a signal controller that transmits an image signal having an embedded clock signal;
a data driver includes:
a clock data recovery (CDR) circuit that recovers from the image data a first internal reference clock signal during an off period of a first frame control signal and when a second frame control signal corresponds to a previously set CDR circuit operating condition, the CDR circuit recovers a second internal reference clock signal; a memory unit stores a frequency of a preset reference clock signal; a comparator compares the frequency of the recovered first internal reference clock signal with the frequency of the preset reference clock signal, outputs the frequency of the recovered first internal reference clock signal, and receives a second frame control signal when the frequency of the recovered first internal reference clock signal is within an error range of the frequency of the preset reference clock signal.

17. The display device of claim 16 , further comprising a pulse counter determines the number of inactive period of the second frame control signal within a sequence corresponds to and sets the pulse counter to the determined number of times, determines whether the pulse counter is identical

Assignees

• Samsung Display Co Ltd

Inventors

• Lim Woon Yong
• Pyun Ki Hyun

Classifications

• G09G5/18 Primary

  Timing circuits for raster scan displays (specially adapted for television H04N {; synchronisation between the display unit and other display units, videodisc player G09G5/12}) · CPC title

• G09G2310/0294

  Details of sampling or holding circuits arranged for use in a driver for data electrodes · CPC title

• G09G2330/06

  Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation · CPC title

• G09G3/20

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G5/008

  Clock recovery · CPC title