Managed instruction cache prefetching

Patent metadata

Field	Value
Publication number	US-9811341-B2
Application number	US-201113995649-A
Country	US
Kind code	B2
Filing date	Dec 29, 2011
Priority date	Dec 29, 2011
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

Disclosed is an apparatus and method to manage instruction cache prefetching from an instruction cache. A processor may comprise: a prefetch engine; a branch prediction engine to predict the outcome of a branch; and dynamic optimizer. The dynamic optimizer may be used to control: identifying common instruction cache misses and inserting a prefetch instruction from the prefetch engine to the instruction cache.

First claim

What is claimed is:

1. A method to manage instruction cache prefetching from an instruction cache comprising:
storing information about instruction cache misses, wherein the information includes an instruction cache line address, branch target characteristics including a type of branch indicator, the confidence of the prediction, and a branch address;
identifying common instruction cache misses; predicting the outcome of a branch and providing a confidence of the prediction;
for an indirect branch, inserting, regardless of the confidence, a prefetch instruction from a prefetch engine to the instruction cache; and
for a direct branch, inserting the prefetch instruction from the prefetch engine to the instruction cache is based upon whether the taken branch had a strong prediction or a weak prediction and the prefetch instruction is executed or not executed dependent upon the confidence of the prediction.

2. A processor to manage instruction cache prefetching from an instruction cache comprising:
a prefetch engine;
a branch prediction engine to predict the outcome of a branch and provide a confidence of the prediction; and
a dynamic optimizer to control:
storing information about cache misses, wherein the information includes an instruction cache line address, branch target characteristics including a type of branch indicator, the confidence of the prediction, and a branch address;
identifying common instruction cache misses;
for an indirect branch, to insert, regardless of the confidence, a prefetch instruction from the prefetch engine to the instruction cache; and
for a direct branch, to insert a prefetch instruction from the prefetch engine to the instruction cache is based upon whether the taken branch had a strong prediction or a weak prediction and the prefetch instruction is executed or not executed dependent upon the confidence of the prediction.

3. A computer system comprising:
a memory control hub coupled to a memory; and
a processor to manage instruction cache prefetching comprising:
a prefetch engine; a branch prediction engine to predict the outcome of a branch and provide a confidence of the prediction; and
a dynamic optimizer to control:
storing information about cache misses, wherein the information includes an instruction cache line address, branch target characteristics characteristics including a type of branch indicator, the confidence of the prediction, and a branch address;
identifying common instruction cache misses;
for an indirect branch, inserting, regardless of the confidence, a prefetch instruction from the prefetch engine to the instruction cache; and
for a direct branch, inserting the prefetch instruction from the prefetch engine to the instruction cache is based upon whether the taken branch had a strong prediction or a weak prediction and the prefetch instruction is executed or not executed dependent upon the confidence of the prediction.

4. A computer program product comprising:
a non-transitory computer-readable medium comprising code for:
storing information about instruction cache misses, wherein the information includes an instruction cache line address, branch target characteristics including a type of branch indicator, the confidence of the prediction, and a branch address;
identifying common instruction cache misses; predicting the outcome of a branch and providing a confidence of the prediction; and
for an indirect branch, inserting, regardless of the confidence, a prefetch instruction from a prefetch engine to the instruction cache; and
for a direct branch, inserting the prefetch instruction from the prefetch engine to the instruction cache is based upon whether the taken branch had a strong prediction or a weak prediction and the prefetch instruction is executed or not executed dependent upon the confidence of the prediction.

5. The computer program product of claim 4 , further comprising code for creating a table to store profiled information including at least an address of an instruction missed in the instruction cache.

Assignees

• Stavrou Kyriakos A
• Gibert Codina Enric
• Codina Josep M
• Gomez Requena Crispin
• Gonzalez Antonio
• Hyuseinova Mirem
• Kotselidis Christos E
• Latorre Fernando
• Lopez Pedro
• Lupon Marc
• Madriles Gimeno Carlos
• Magklis Grigorios
• Marcuello Pedro
• Martinez Vicente Alejandro
• Martinez Raul
• Ortega Daniel
• Pavlou Demos
• Tournavitis Georgios
• Xekalakis Polychronis
• Intel Corp

Inventors

• Stavrou Kyriakos A
• Gibert Codina Enric
• Codina Josep M
• Gomez Requena Crispin
• Gonzalez Antonio
• Hyuseinova Mirem
• Kotselidis Christos E
• Latorre Fernando
• Lopez Pedro
• Lupon Marc
• Madriles Gimeno Carlos
• Magklis Grigorios
• Marcuello Pedro
• Martinez Vicente Alejandro
• Martinez Raul
• Ortega Daniel
• Pavlou Demos
• Tournavitis Georgios
• Xekalakis Polychronis

Classifications

• G06F9/3802

  Instruction prefetching · CPC title

• G06F12/0862

  with prefetch · CPC title

• G06F9/30047 Primary

  Prefetch instructions; cache control instructions · CPC title

• G06F9/3804 Primary

  for branches, e.g. hedging, branch folding · CPC title

• G06F9/3017

  Runtime instruction translation, e.g. macros · CPC title