Semiconductor device, diagnostic test, and diagnostic test circuit

Patent metadata

Field	Value
Publication number	US-9810738-B2
Application number	US-201514676743-A
Country	US
Kind code	B2
Filing date	Apr 1, 2015
Priority date	Apr 11, 2014
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

Deterioration in operation performance due to a fault diagnosis is prevented. A semiconductor device 90 according to the present invention includes a plurality of CPU cores 91 to 94 each including a scan chain, and a diagnostic test circuit 95 that performs a scan test for the plurality of CPU cores 91 to 94 by using the scan chain of the CPU core. The diagnostic test circuit 95 performs a scan test for each of the plurality of CPU cores 91 to 94 in a predetermined order on a periodic basis so that execution time periods of the scan tests do not overlap each other.

First claim

What is claimed is:

1. A semiconductor device comprising:
a plurality of CPU (Central Processing Unit) cores each comprising a scan chain; and
a diagnostic test circuit that performs a scan test for the plurality of CPU cores by using the scan chain in each of the CPU cores, wherein
the diagnostic test circuit performs a scan test for each of the plurality of CPU cores in a predetermined order so that execution time periods of the scan tests do not overlap each other,
the scan test for each of the plurality of CPU cores is repeated periodically until the diagnostic test circuit determines that there is a failure in the plurality of CPU cores, and
during an execution time period of the scan test for one of the plurality of CPU cores, the rest of the plurality of CPU cores perform normal operations.

2. The semiconductor device according to claim 1 , further comprising an interrupt circuit that generates an interruption for each of the plurality of CPU cores, wherein
each of the plurality of CPU cores outputs an instruction signal indicating a start of the scan test in response to the interruption, and
the diagnostic test circuit performs a scan test for each of the plurality of CPU cores in response to the output of the instruction signal from a respective one of the plurality of CPU cores.

3. The semiconductor device according to claim 2 , wherein
each of the plurality of CPU cores executes a program scheduled by an operating system, and
each of the plurality of CPU cores interrupts, when the interruption is generated, execution of the program currently executed by the CPU core itself to bring the program into an execution waiting state and performs setting so that the operating system does not schedule an arbitrary program for the that CPU core.

4. The semiconductor device according to claim 3 , further comprising a record information storage unit that stores, when each of the CPU cores outputs the instruction signal to the diagnostic test circuit, record information indicating that the instruction signal is output from each of the CPU cores, wherein
each of the plurality of CPU cores checks, when the record information is stored in the record information storage unit after a scan test is performed in that CPU core itself, an execution result of that scan test, and when an abnormality is detected, prevents setting for restoring the scheduling for allowing an arbitrary program to be scheduled for that CPU core.

5. The semiconductor device according to claim 3 , wherein
the interrupt circuit is a system timer that generates a timer interruption as the interruption in a predetermined interrupt cycle,
the semiconductor device further comprises a time information storage unit that stores, when each of the plurality of CPU cores outputs the instruction signal to the diagnostic test circuit, a time information indicating a time at that moment, the time information being stored into the time information storage unit by a respective one of the plurality of CPU cores,
each of the plurality of CPU cores prevents, when a difference between a time acquired from the system timer after a scan test is performed in that CPU core itself and a time indicated by the time information stored in the time information storage unit is greater than a predetermined threshold, setting for restoring the scheduling for allowing an arbitrary program to be scheduled for that CPU core.

6. The semiconductor device according to claim 2 , wherein
the interrupt circuit is a system timer that generates a timer interruption as the interruption in a predetermined interrupt cycle,
the semiconductor device further comprises a time information storage unit that stores, when each of the plurality of CPU cores outputs the instruction signal to the diagnostic test circuit, a time information indicating a time at that moment, the time information being stored into the time information storage unit by a respective one of the plurality of CPU cores,
each of the CPU core outputs the instruction signal to the diagnostic test circuit when a difference between a time acquired from the system timer in an interrupt process performed in response to the timer interruption and a time indicated by the time information stored in the time information storage unit reaches an execution period of the scan test.

7. The semiconductor device according to claim 2 , wherein
the diagnostic test circuit initializes each of the plurality of CPU cores after the scan test for a respective one of the plurality of CPU cores is performed, and
the semiconductor device further comprises:
a storage unit that stores an instruction in an interrupt process executed in response to the interruption; and
a reset controller that changes an address at which each of the plurality of CPU cores reads an instruction in response to the initialization from a reset vector to an address of an instruction at which the execution by the CPU core is interrupted due to the scan test in the interrupt process.

8. The semiconductor device according to claim 2 , wherein the interrupt circuit is a diagnostic test trigger circuit that generates the interruption for each of the plurality of CPU cores at an execution timing of the scant test performed in a respective one of the plurality of CPU cores.

9. The semiconductor device according to claim 1 , wherein
the diagnostic test circuit successively supplies a plurality of input test data to a currently-diagnosed CPU core through the scan chain,
the currently-diagnosed CPU core successively outputs a plurality of output result data to the diagnostic test circuit through the scan chain, each of the plurality of output result data being generated based on a respective one of the plurality of supplied input test data,
the diagnostic test circuit diagnoses the currently-diagnosed CPU core by reading a first cumulative calculation result from a test data storage unit storing the plurality of input test data and the first cumulative calculation result and comparing the read first cumulative calculation result with a second cumulative calculation result, the first cumulative calculation result being an expected value of a cumulative calculation result of the plurality of output result data, the second cumulative calculation result being obtained by cumulatively calculating the plurality of output result data successively output from the currently-diagnosed CPU core.

10. The semiconductor device according to claim 1 , further comprising a DMA controller connected to the diagnostic test circuit through a system bus, the DMA controller being configured to acquire a plurality of input test data from a test data storage unit and successively DMA-transfer the acquired input test data to the diagnostic test circuit through the system bus, the test data storage unit being configured to store the plurality of input test data, the plurality of input test data being successively supplied to the scan chain in the scan test, wherein
the diagnostic test circuit comprises a FIFO memory that temporarily stores a part of the plurality of input test data, acquires the input test data stored in the FIFO memory, and supplies the acquired input test data to the currently-diagnosed CPU core through the scan chain.

11. The semiconductor device according to claim 1 , further comprising a second diagnostic test circuit that performs a test for the diagnostic test circuit before the diagnostic test circuit starts a scan test for the plurality of CPU cores.

12. The semiconductor device according to claim 1 , wherein
when the diagnostic test circuit performs the scan test, the diagnostic test circuit acquires the input test data from a test da

Assignees

• Renesas Electronics Corp

Inventors

• Tsuboi Yukitoshi
• Nagano Hideo
• Nagaoka Hiroshi
• Matsunaga Yusuke
• Igaku Yutaka
• Kubota Naotaka

Classifications

• G06F11/08

  Error detection or correction by redundancy in data representation, e.g. by using checking codes · CPC title

• G01R31/318544 Primary

  Scanning methods, algorithms and patterns (G01R31/3183 takes precedence) · CPC title

• G01R31/3177 Primary

  Testing of logic operation, e.g. by logic analysers · CPC title