DDR addressable TAP interface with shadow protocol and TAP domain

Patent metadata

Field	Value
Publication number	US-9170299-B2
Application number	US-201414508526-A
Country	US
Kind code	B2
Filing date	Oct 7, 2014
Priority date	Oct 20, 2006
Publication date	Oct 27, 2015
Grant date	Oct 27, 2015

Abstract

A process and apparatus provide a JTAG TAP controller ( 302 ) to access a JTAG TAP domain ( 106 ) of a device using a reduced pin count, high speed DDR interface ( 202 ). The access is accomplished by combining the separate TDI and TMS signals from the TAP controller into a single signal and communicating the TDI and TMS signals of the single signal on the rising and falling edges of the TCK driving the DDR interface. The TAP domain may be coupled to the TAP controller in a point to point fashion or in an addressable bus fashion. The access to the TAP domain may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

First claim

What is claimed is:

1. An integrated circuit comprising:
A. a TDI/TMS input lead;
B. a TCK input lead;
C. a TDO output lead;
D. double data rate circuitry having an input coupled to the TDI/TMS input lead, an input coupled to the TCK input lead, and separate TDI and TMS output leads;
E. addressable TAP interface circuitry having:
i. a TDI input coupled to the TDI output lead;
ii. a TMS input coupled to the TMS output lead;
iii. a TCK input coupled to the TCK input lea…

Assignees

• Texas Instruments Inc

Inventors

• Whetsel Lee D

Classifications

• G01R31/318544 Primary

  Physics · mapped topic

• G01R31/3177 Primary

  Physics · mapped topic

• G01R31/318547

  Physics · mapped topic

• G11C29/48

  Physics · mapped topic

• G01R31/2851

  Physics · mapped topic