Apparatus and methods for radio frequency amplifiers

Patent metadata

Field	Value
Publication number	US-9806680-B2
Application number	US-201615265047-A
Country	US
Kind code	B2
Filing date	Sep 14, 2016
Priority date	May 10, 2011
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

Apparatus and methods for radio frequency (RF) amplifiers are disclosed herein. In certain implementations, a packaged RF amplifier includes a first bipolar transistor including a base electrically connected to an RF input pin and a collector electrically connected to an RF output pin, and a second bipolar transistor including a base electrically connected to an emitter of the first bipolar transistor and a collector electrically connected to the RF output pin. The packaged RF amplifier further includes a first bias circuit electrically connected between the base of the first bipolar transistor and the RF output pin, a second bias circuit electrically connected between the base of the first bipolar transistor and a power low pin, an inductor implemented at least partly by a bond wire, and a third bias circuit electrically connected in series with the inductor between the base of the second bipolar transistor and the power low pin.

First claim

What is claimed is:

1. A packaged integrated circuit comprising:
a die attach paddle configured to receive a ground voltage;
a die attached to the die attach paddle and including an amplifier that includes a first bipolar transistor, a second bipolar transistor, and a first bias circuit, the first bipolar transistor including an emitter electrically connected to a base of the second bipolar transistor; and
a bond wire connected between the die attach paddle and the die, the emitter of the first bipolar transistor configured to receive the ground voltage via the first bias circuit and the bond wire.

2. The packaged integrated circuit of claim 1 wherein the die further includes a through-wafer via electrically connected to the die attach paddle and configured to provide the ground voltage to one or more electrical components of the amplifier.

3. The packaged integrated circuit of claim 2 wherein the amplifier further includes a second bias circuit, an emitter of the second bipolar transistor configured to receive the ground voltage via the second bias circuit and the through-wafer via.

4. The packaged integrated circuit of claim 2 wherein the first bias circuit includes a diode and a resistor electrically connected in series.

5. The packaged integrated circuit of claim 4 wherein the diode is implemented with a transistor connected in a diode configuration.

6. The packaged integrated circuit of claim 2 wherein the amplifier further includes an input bias circuit, a base of the first bipolar transistor configured to receive the ground voltage via the input bias circuit and the through-wafer via.

7. The packaged integrated circuit of claim 6 wherein the input bias circuit includes a first diode, a second diode, and a resistor electrically connected in series.

8. The packaged integrated circuit of claim 1 wherein the bond wire passes over more than half of a length of the die.

9. A mobile device comprising:
one or more antennas;
a plurality of switches electrically connected to the one or more antennas; and
a transceiver electrically connected to the plurality of switches and including a packaged integrated circuit configured to provide amplification to a radio frequency signal received from the plurality of switches, the packaged integrated circuit including a die attach paddle configured to receive a ground voltage, a die attached to the die attach paddle, and a bond wire connected between the die attach paddle and the die, the die including an amplifier that includes a first bipolar transistor, a second bipolar transistor, and a first bias circuit, the first bipolar transistor including an emitter electrically connected to a base of the second bipolar transistor and configured to receive the ground voltage via the first bias circuit and the bond wire.

10. The mobile device of claim 9 wherein the die further includes a through-wafer via electrically connected to the die attach paddle and configured to provide the ground voltage to one or more electrical components of the amplifier.

11. The mobile device of claim 10 wherein the amplifier further includes a second bias circuit, an emitter of the second bipolar transistor configured to receive the ground voltage via the second bias circuit and the through-wafer via.

12. The mobile device of claim 10 wherein the first bias circuit includes a diode and a resistor electrically connected in series.

13. A packaged integrated circuit comprising:
a die attach paddle configured to receive a ground voltage;
a die attached to the die attach paddle and including an amplifier that includes a first field effect transistor, a second field effect transistor, and a first bias circuit, the first field effect transistor including a source electrically connected to a gate of the second field effect transistor; and
a bond wire connected between the die attach paddle and the die, the source of the first field effect transistor configured to receive the ground voltage via the first bias circuit and the bond wire.

14. The packaged integrated circuit of claim 13 wherein the die further includes a through-wafer via electrically connected to the die attach paddle and configured to provide the ground voltage to one or more electrical components of the amplifier.

15. The packaged integrated circuit of claim 14 wherein the amplifier further includes a second bias circuit, a source of the second field effect transistor configured to receive the ground voltage via the second bias circuit and the through-wafer via.

16. The packaged integrated circuit of claim 14 wherein the first bias circuit includes a diode and a resistor electrically connected in series.

17. The packaged integrated circuit of claim 16 wherein the diode is implemented with a transistor connected in a diode configuration.

18. The packaged integrated circuit of claim 14 wherein the amplifier further includes an input bias circuit, a gate of the first field effect transistor configured to receive the ground voltage via the input bias circuit and the through-wafer via.

19. The packaged integrated circuit of claim 18 wherein the input bias circuit includes a first diode, a second diode, and a resistor electrically connected in series.

20. The packaged integrated circuit of claim 13 wherein the bond wire passes over more than half of a length of the die.

Assignees

• Skyworks Solutions Inc

Inventors

• Ake Alan William
• Dening David C

Classifications

• H10W72/5449

  not being orthogonal to a side surface of the chip, e.g. fan-out arrangements · CPC title

• H10W72/5473

  multiple bond wires connected to a common bond pad · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/932

  Plan-view shape, i.e. in top view · CPC title

• H10W44/226

  for HF amplifiers · CPC title