Analog/digital converter with charge rebalanced integrator

Patent metadata

Field	Value
Publication number	US-9806552-B2
Application number	US-201615169981-A
Country	US
Kind code	B2
Filing date	Jun 1, 2016
Priority date	Feb 15, 2016
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

A charge rebalancing integration circuit can help keep an output node of a front-end integration circuit within a specified range, e.g., without requiring resetting of the integration capacitor. The process of monitoring and rebalancing the integration circuit can operate on a much shorter time base than the integration time period, which can allow for multiple charge balancing charge transfer events during the integration time period, and sampling of the integration capacitor once per integration time period, such as at the end of that integration time period. Information about the charge rebalancing can be used to adjust subsequent discrete-time signal processing, such as digitized values of the samples. Improved dynamic range and noise performance is possible. Computed tomography (CT) imaging and other use cases are described, including those with variable integration periods.

First claim

The claimed invention is:

1. A system for sampling a wide-dynamic range analog input signal onto an integration capacitor for conversion into a digital signal, the system comprising:
a front-end interface circuit including:
an an integration capacitor for sampling the input signal once per an integration time period; and
a conditional charge transfer circuit, coupled to the integration capacitor,
to transfer, when the signal on the integration capacitor extends outside a range, a specified quantity of charge on the integration capacitor in a charge transfer event such that the signal on the integration capacitor returns within the range; and
a notification circuit that provides notification of one or more charge transfer events during the same integration time period to permit adjustment of a digital signal value generated using the signal on the integration capacitor to account for the one or more charge transfer events.

2. The system of claim 1 , further comprising:
an analog-to-digital converter circuit, coupled to the integration capacitor to receive an analog signal and to convert the analog signal into a digital signal.

3. The system of claim 2 , wherein the charge transfer circuit is configured to conditionally trigger charge transfer events that are temporally separated by at least a specified charge transfer period that is shorter than the integration period, and wherein the charge transfer event occurs without resetting the integration capacitor to a specified voltage.

4. The system of claim 1 , wherein the charge transfer circuit includes a specified current source operating for a specified time duration to provide the specified quantity of charge transferred by the charge transfer circuit on the integration capacitor during the charge transfer event.

5. The system of claim 1 , wherein the charge transfer circuit includes a charge transfer capacitor having a specified charge state, coupled by a switch to the integration capacitor to provide the specified quantity of charge transferred by the charge transfer circuit on the integration capacitor via the amplifier first input node during the charge transfer event.

6. The system of claim 5 , comprising:
a plurality of specified threshold levels; and
wherein the charge transfer capacitor includes a selected one or more capacitors from a group of capacitors to provide a programmably selectable capacitance value of the charge transfer capacitor based on which one of the specified threshold levels was crossed by the integration capacitor signal.

7. The system of claim 5 , wherein the charge transfer events are conditionally determined recurrently at a specified charge transfer frequency, and wherein the charge transfer capacitor is discharged to other than the integration capacitor at recurrences at which a charge transfer event is contraindicated.

8. The system of claim 1 , wherein the conditional charge transfer circuit is configured to return a signal on the integration capacitor within a range that includes both upper and lower bounds.

9. The system of claim 8 , wherein the notification circuit includes:
a counter circuit to count, over an integration period of the integration capacitor, a first count of specified quantities of charge added on the integration capacitor and a second count of specified quantities of charge subtracted from the integration capacitor; and
a difference circuit, to take a difference of the first and second counts to provide an indication of a net specified quantity of charge added to or subtracted from the integration capacitor during the integration period, to provide an adjustment value to permit adjustment of a digital signal value, corresponding to the integration period, provided by the analog-to-digital converter circuit to account for the one or more charge transfer events during the same integration period.

10. The system of claim 1 , wherein the first threshold value is adjustable and dithered.

11. The system of claim 10 , further comprising a photodiode, coupled to the front-end interface circuit such that a charge from the photodiode is integrated onto the integration capacitor during the integration period.

12. The system of claim 10 , further comprising a computed tomography (CT) detection receiver circuit, coupled to the front-end interface circuit such that charge from the CT detection receiver circuit is integrated onto the integration capacitor during the integration period.

13. The system of claim 10 , comprising a multiplexer circuit that time-multiplexes a back-end discrete time circuit between multiple front-end interface circuits.

14. The system of claim 1 , wherein the integration time period is variable between successive integration periods.

15. The system of claim 1 , wherein a duration of the integration time period is capable of being specified during that same particular integration time period.

16. A system for sampling a wide-dynamic range analog input signal onto an integration capacitor for conversion into a digital signal, the system comprising:
a front-end interface circuit for an analog-to-digital converter circuit, the front-end interface circuit including:
an integration capacitor, wherein the integration circuit integrates charge from a received input signal onto the integration capacitor over an integration time period for being sampled once per integration time period; and
a conditional charge transfer circuit, coupled to the integration capacitor, the conditional charge transfer circuit including:
a range bounded by a specified first threshold level and a specified second threshold level;
a charge transfer circuit to transfer, when the signal at the integration capacitor crosses the specified first threshold level, a specified quantity of charge on the integration capacitor in a charge transfer event such that the signal at the integration capcitor re-crosses the specified first threshold level in the other direction, and, to transfer, when the signal at the integration capacitor crosses the specified second threshold level, a specified quantity of charge on the integration capacitor in a charge transfer event such that the signal at the integration capacitor re-crosses the specified second threshold level in the other direction,

an analog-to-digital converter circuit, coupled to the amplifier circuit output node to receive an analog signal and to convert the analog signal into a digital signal; and
wherein the charge transfer event occurs without resetting the integration capacitor to a specified voltage, and further comprising a notification circuit that provides notification of one or more charge transfer events to permit adjustment of a digital signal value provided by the analog-to-digital converter circuit to account for a net charge provided to the integration capacitor during one or more charge transfer events occurring during the same integration period of the integration capacitor.

17. A method comprising:
receiving an input signal;
integrating, onto an integration capacitor over an integration time period for being sampled once per integration time period, a charge provided by the input signal;
determining, more often than once per integration period, whether an integration capacitor signal exceeds a specified first threshold level;
when it is determined that the integration capacitor signal exceeds the specified first threshold level, transferring a specified quantity of charge on the integration capacitor such that the integration capacitor signal no longer exceeds the specified first threshold level;
providing a sampl

Assignees

• Analog Devices Global

Inventors

• Brannick Paraic
• Lyden Colin G
• Mccartney Damien J
• Banarie Gabriel

Classifications

• H03M1/54

  Input signal sampled and held with linear return to datum · CPC title

• G01N2223/305

  computer simulations · CPC title

• H03M1/52

  Input signal integrated with linear return to datum · CPC title

• G01N2223/304

  electric circuits, signal processing · CPC title

• G01N23/046

  using tomography, e.g. computed tomography [CT] · CPC title