Power MOSFET device structure for high frequency applications

Patent metadata

Field	Value
Publication number	US-9806175-B2
Application number	US-201514629229-A
Country	US
Kind code	B2
Filing date	Feb 23, 2015
Priority date	May 9, 2005
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite the first surface. The switching device further includes an insulated gate electrode disposed on top of the second surface for controlling a source to drain current. The switching device further includes a source electrode interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region. The semiconductor substrate further includes an epitaxial layer disposed above and having a different dopant concentration than the drain region. The insulated gate electrode further includes an insulation layer for insulating the gate electrode from the source electrode wherein the insulation layer having a thickness depending on a Vgsmax rating of the vertical power device.

First claim

We claim:

1. A method for manufacturing a power MOSFET device in a semiconductor substrate comprising:
implanting a JFET (junction field effect transistor) region of a first conductivity type in an upper portion of the semiconductor substrate followed by growing a gate oxide layer on a top surface of the semiconductor substrate then depositing a gate layer on top of the gate oxide layer followed by applying a gate mask to etch and pattern the gate layer into a plurality of planar gates on the top surface of the semiconductor substrate wherein each of the planar gates is patterned into two split gate segments separated by a segment gap;
implanting body regions of a second conductivity type in the upper portion of the semiconductor substrate with a top surface of the body region surrounding a bottom surface of the planar gate followed by applying a source mask to implant source regions encompassed by the body regions;
depositing an inter-layer insulation layer covering over an entire top surface of the MOSFET device wherein the insulation layer forming a dip slot over each of the segment gaps separating the split gate segments wherein the dip slot vertically extending below a top surface of the split gate segments; and
applying contact trench mask for opening a plurality of source contact trenches and opening a plurality of gate contact trenches through the inter-layer insulation layer followed by depositing a top metal layer and patterning the top metal layer into a source metal with the source metal filling the dip slots of the insulation layer formed between the split gate segments wherein the source metal filling the dip slots vertically extending below a top surface of the split gate segments.

2. The method of claim 1 further comprising:
applying a metal mask for patterning the top metal layer into a gate metal for contacting said planar gates through the gate contact trenches.

3. The method of claim 1 wherein:
the step of applying the contact trench mask for opening the source contact trenches further comprising a step of opening the source contact trenches to vertically extend into an upper portion of the body and source regions for the source metal to vertically extend into the source and body regions below the top surface of the semiconductor substrate.

4. The method of claim 1 wherein:
said step of opening the source contact trenches comprising a step of implant a heavily doped contact region of the second conductivity type below the source contact trenches for enhancing an electrical contact between the source metal to the source regions and the body regions.

5. The method of claim 1 wherein:
said step of opening the gate contact trenches through the inter-layer insulation layer further comprising a step of opening a drain contact trench through the inter-layer insulation layer in a termination area; and
the step of depositing the top metal layer and patterning the top metal layer into the source metal further comprising a step of patterning the top metal layer into a channel stop in the termination area with the channel stop vertically extended into the drain contact trench for electrically connecting to a drain of the power MOSFET device through the semiconductor substrate.

6. The method of claim 1 wherein:
the method for manufacturing the power MOSFET device further comprising a step of manufacturing said power MOSFET device as an N-channel MOSFET device.

7. The method of claim 1 wherein:
the method for manufacturing the power MOSFET device further comprising a step of manufacturing said power MOSFET device as an P-channel MOSFET device.

Assignees

• Bhalla Anup
• Ng Daniel
• Li Tiesheng
• Lui Sik K
• Alpha & Omega Semiconductor

Inventors

• Bhalla Anup
• Ng Daniel
• Li Tiesheng
• Lui Sik K

Classifications

• H10D64/2527

  for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies · CPC title

• H01L29/1095

  Electricity · mapped topic

• H01L29/42368

  Electricity · mapped topic

• H01L29/66727

  Electricity · mapped topic

• H01L29/66719

  Electricity · mapped topic