High voltage multiple channel LDMOS

Patent metadata

Field	Value
Publication number	US-9806074-B2
Application number	US-201514965182-A
Country	US
Kind code	B2
Filing date	Dec 10, 2015
Priority date	Dec 29, 2013
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

An integrated circuit and method having an LDMOS transistor with multiple current channels. A first current channel is above a buried p-type diffusion and a second one current channel is below the buried p-type diffusion.

First claim

What is claimed is:

1. An integrated circuit, comprising:
an NMOS transistor;
a PMOS transistor;
a lateral diffused metal-oxide-semiconductor (LDMOS) transistor with a gate, source, drain and at least two current channels coupled between the source and the drain; and
wherein the gate switches current in the current channels, wherein
the LDMOS transistor is an n-channel LDMOS(LDNMOS) transistor;
the at least two current channels are horizontal current channels;
a first horizontal current channel is formed in a first lateral doped n-type diffusion beneath a top p-type diffusion and above a buried p-type diffusion; and
a second horizontal current channel is formed in a buried n-type diffusion beneath the buried p-type diffusion and above a p-type substrate.

2. The integrated circuit of claim 1 , wherein the gate comprises a first gate structure and a second gate structure.

3. The integrated circuit of claim 1 , wherein the buried p-type diffusion has a lower dopant concentration near a drain end of the LDMOS than near a source end of the LDMOS.

4. The integrated circuit of claim 1 , wherein the top p-type diffusion is located below a shallow trench isolation geometry.

5. An integrated circuit, comprising:
an NMOS transistor;
a PMOS transistor;
a lateral diffused metal-oxide-semiconductor (LDMOS) transistor with a gate, source, drain and at least two current channels coupled between the source and the drain; and
wherein the gate switches current in the current channels, wherein
the LDMOS transistor is a p-channel LDMOS (LDPMOS) transistor;
the at least two current channels are horizontal current channels;
a first horizontal current channel is formed in a first lateral doped p-type diffusion beneath a top n-type diffusion and above a buried n-type diffusion; and
a second horizontal current channel is formed in a buried p-type diffusion beneath the buried n-type diffusion and above an n-type substrate.

6. The integrated circuit of claim 5 , wherein the gate comprises a first gate structure and a second gate structure.

7. The integrated circuit of claim 5 , wherein the buried n-type diffusion has a lower dopant concentration near a drain end of the LDMOS than near a source end of the LDMOS.

8. The integrated circuit of claim 5 , wherein the top n-type diffusion is located below a shallow trench isolation geometry.

9. An integrated circuit, comprising:
an NMOS transistor;
a PMOS transistor;
a lateral diffused metal-oxide-semiconductor (LDMOS) transistor with a first gate, with source, a drain and at least two current channels coupled between the source and the drain; and
a second LDMOS transistor with a second gate wherein the first and second LDMOS transistors share the source and the drain and wherein current from the second LDMOS transistor flows through at least one of the current channels;
wherein the first and second gates switch current in the current channels; wherein
the first LDMOS transistor is an n-channel LDMOS (LDNMOS) transistor and wherein the second LDMOS transistor is a LDNMOS transistor;
the at least two current channels are horizontal current channels;
a first horizontal current channel is formed in lateral doped n-type diffusion beneath a top p-type diffusion and above a buried p-type diffusion;
a second horizontal current channel is formed in a buried n-type diffusion beneath the buried p-type diffusion and above a p-type substrate;
the first LDNMOS transistor switches a first current in the first horizontal current channel and the first current in the second horizontal channel; and
the second LDNMOS transistor switches a second current in the second horizontal current channel.

10. An integrated circuit, comprising:
an NMOS transistor;
a PMOS transistor;
a lateral diffused metal-oxide-semiconductor (LDMOS) transistor with a first gate, a source, a drain and at least two current channels coupled between the source and the drain; and
a second LDMOS transistor with a second gate wherein the first and second LDMOS transistors share the source and the drain and wherein current from the second LDMOS transistor flows through at least one of the current channels;
wherein the first and second gates switch current in the current channels, wherein
the first LDMOS transistor is a p-channel LDMOS (LDPMOS) transistor and wherein the second LDMOS transistor is a LDPMOS transistor;
the at least two current channels are horizontal current channels;
a first horizontal current channel is formed in lateral doped p-type diffusion beneath a top n-type diffusion and above a buried n-type diffusion;
a second horizontal current channel is formed in a buried p-type diffusion beneath the buried n-type diffusion and above a n-type substrate;
the first LDPMOS transistor switches a first current in the first horizontal current channel and switches the first current in the second horizontal channel; and
the second LDPMOS transistor switches a second current in the second horizontal current channel.

11. An integrated circuit, comprising:
an NMOS transistor;
a PMOS transistor;
a lateral diffused metal-oxide-semiconductor (LDMOS) transistor with a gate, with a source, a drain, a first horizontal current path between the source and drain and a second horizontal current path between the source and drain, wherein the first horizontal current path is formed in a first lateral doped diffusion of a first conductivity type beneath a top diffusion of a second conductivity type and above a buried diffusion of the second conductivity type and the second horizontal current path is formed in a buried diffusion of the first conductivity type beneath the buried diffusion of the second conductivity type and above a substrate of the second conductivity type.

12. The integrated circuit of claim 11 , wherein the first conductivity type is n-type and the second conductivity type is p-type.

13. The integrated circuit of claim 11 , wherein the first conductivity type is p-type and the second conductivity type is n-type.

14. The integrated circuit of claim 11 , wherein the gate comprises a first gate structure and a second gate structure.

15. The integrated circuit of claim 11 , wherein the buried diffusion of the second conductivity type has a lower dopant concentration near a drain end of the LDMOS than near a source end of the LDMOS.

16. The integrated circuit of claim 11 , wherein the top diffusion of the second conductivity type is located below a shallow trench isolation geometry.

Assignees

• Texas Instruments Inc

Inventors

• Zhang Yongxi
• Pendharkar Sameer P

Classifications

• H10P32/1406

  by ion implantation · CPC title

• H10P32/171

  being group IV material · CPC title

• H10P30/22

  using masks · CPC title

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title