Reinforced wafer level package comprising a core layer for reducing stress in a solder joint and improving solder joint reliability

Patent metadata

Field	Value
Publication number	US-9806063-B2
Application number	US-201514699863-A
Country	US
Kind code	B2
Filing date	Apr 29, 2015
Priority date	Apr 29, 2015
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

Some features pertain to a package that includes a redistribution portion, a first die coupled to the redistribution portion, a core layer coupled to the redistribution portion, and an encapsulation layer encapsulating the first die and the core layer. The redistribution portion includes a first dielectric layer. The core layer has a higher Young's Modulus than the encapsulation layer. In some implementations, the core layer includes a glass fiber (e.g., core layer is a glass reinforced dielectric layer). In some implementations, the core layer has a Young's Modulus of about at least 15 gigapascals (Gpa). In some implementations, the first die includes a front side and a back side, where the front side of the first die is coupled to the redistribution portion. In some implementations, the first dielectric layer is a photo imageable dielectric (PID) layer.

First claim

What is claimed is:

1. A package comprising:
a redistribution portion comprising:
a first photo imageable dielectric (PID) layer; and
a first interconnect, wherein the first interconnect comprises a first via in the first photo imageable dielectric (PID) layer, wherein the first via comprises a diameter of about 30 (μm) microns or less;

a first die comprising a pad, the first die coupled to the redistribution portion, wherein the first die is coupled to the first interconnect of the redistribution portion such that the pad is directly touching the first interconnect of the redistribution portion;
a core layer coupled to the redistribution portion; and
an encapsulation layer encapsulating the first die and the core layer.

2. The package of claim 1 , wherein the core layer has a first Young's Modulus, and the encapsulation layer has a second Young's Modulus, wherein the first Young's Modulus is greater than the second Young's Modulus.

3. The package of claim 2 , wherein the first Young's Modulus is about at least 15 gigapascals (Gpa) or greater.

4. The package of claim 2 , wherein the second Young's Modulus is less than about 15 gigapascals (Gpa).

5. The package of claim 1 , wherein the core layer comprises a glass fiber.

6. The package of claim 1 , wherein the first die comprises a front side and a back side, wherein the front side of the first die is coupled to the redistribution portion.

7. The package of claim 1 , wherein the encapsulation layer has a coefficient of thermal expansion (CTE) in the range of about 20-50 parts per million per degree Celsius (ppm/C).

8. The package of claim 1 , wherein the core layer has a coefficient of thermal expansion (CTE) that is less than about 12 parts per million per degree Celsius (ppm/C).

9. The package of claim 1 , wherein the package is a fan-out wafer level package.

10. The package of claim 1 , wherein the core layer includes a via.

11. The package of claim 1 , wherein the encapsulation layer comprises an encapsulation interconnect.

12. The package of claim 1 , wherein the package is integrated in a package on package (PoP) device, the package on package (PoP) device comprising a second package.

13. The package of claim 12 , wherein the second package is a package from a group of packages comprising a fan-out wafer level package (FOWLP), a wire bond chip scale package (CSP), and/or a flip chip chip scale package (CSP).

14. The package of claim 1 , wherein the package is incorporated into a device selected from a group comprising of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in an automotive vehicle, and further including the device.

15. The package of claim 1 , wherein the pad of the first die is coupled to the first interconnect of the redistribution portion such that a coupling between the pad and the first interconnect is free of solder.

16. The package of claim 1 , wherein the first interconnect is an interconnect from a plurality of interconnects formed in the redistribution portion, the plurality of interconnects comprising a pitch of about 30 (μm) microns or less.

17. A package on package (PoP) device comprising:
a first package; and
a second package coupled to the first package, the second package comprising
a redistribution portion comprising:
a first photo imageable dielectric (PID) layer; and
a first interconnect, wherein the first interconnect comprises a first via in the first photo imageable dielectric (PID) layer, wherein the first via comprises a diameter of about 30 (μm) microns or less;

a first die comprising a pad, the first die coupled to the redistribution portion, wherein the first die is coupled to the first interconnect of the redistribution portion such that the pad is directly touching the first interconnect of the redistribution portion;
a core layer coupled to the redistribution portion;
a via traversing the core layer;
an encapsulation layer encapsulating the first die and the core layer; and
a second interconnect in the encapsulation layer, wherein the second interconnect is coupled to the via.

18. The package on package (PoP) device of claim 17 , wherein the second interconnect is a second via in the encapsulation layer, wherein the second via has a diameter of about 40 (μm) microns or greater.

19. The package on package (PoP) device of claim 17 , wherein the second package is a fan-out wafer level package.

20. The package on package (PoP) device of claim 17 , wherein the first package is a package from a group of packages comprising a fan-out wafer level package (FOWLP), a wire bond chip scale package (CSP), and/or a flip chip chip scale package (CSP).

21. The package on package (PoP) device of claim 17 , wherein the redistribution portion further comprises a second dielectric layer, wherein the second dielectric layer is made of a same material as the encapsulation layer, wherein the first photo imageable dielectric (PID) layer is between the encapsulation layer and the second dielectric layer.

22. The package on package (PoP) device of claim 17 , wherein the pad of the first die is coupled to the first interconnect of the redistribution portion such that a coupling between the pad and the first interconnect is free of solder.

23. The package on package (PoP) device of claim 17 , wherein the first interconnect is an interconnect from a plurality of interconnects formed in the redistribution portion, the plurality of interconnects comprising a pitch of about 30 (μm) microns or less.

Assignees

• Qualcomm Inc

Inventors

• Kim Chin-Kwan
• Kumar Rajneesh
• Noveski Vladimir
• Fu Jie
• Syed Ahmer Raza
• Shah Milind Pravin
• Bchir Omar James

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title