System and method for multi-location zapping

Patent metadata

Field	Value
Publication number	US-9805964-B2
Application number	US-201615069943-A
Country	US
Kind code	B2
Filing date	Mar 14, 2016
Priority date	Mar 14, 2016
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

A system for zapping a wafer, the system may include a pulse generation unit that is configured to generate (a) first zapping pulses for causing a breakdown in a first location of a backside insulating layer of a wafer, and (b) second zapping pulses for causing a breakdown in a second location of the backside insulating layer of the wafer; a first conductive interface that is configured to convey the first zapping pulses to the first location, while contacting the first location; a second conductive interface that is configured to convey the second zapping pulses to the second location, while contacting the second location; and wherein the first location differs from the second location.

First claim

What is claimed is:

1. A system for zapping a wafer, the system comprising:
a pulse generation unit that is configured to generate (a) first zapping pulses for causing a breakdown in a first location of a backside insulating layer of a wafer, and (b) second zapping pulses for causing a breakdown in a second location of the backside insulating layer of the wafer different than the first location;
a first conductive interface that is configured to convey the first zapping pulses to the first location, while contacting the first location;
a second conductive interface that is configured to convey the second zapping pulses to the second location, while contacting the second location; and
a controller that is configured to control at least one out of an intensity of the zapping pulses, duration of the zapping pulses and an interval between adjacent zapping pulses.

2. The system according to claim 1 further comprising a sensor that is configured to monitor a coupling between the first conductive interface and the second conductive interface to provide a monitoring result; and wherein the sensor is configured to monitor the coupling occurs while the second conductive interface contacts the second location and the first conductive interface contacts the first location.

3. The system according to claim 1 further comprising a sensor that is configured to monitor a coupling between the first conductive interface and the second conductive interface by sensing electrical signals that pass through the second conductive interface due to the first zapping pulses.

4. The system according to claim 1 further comprising a sensor that is configured to monitor a coupling between the first conductive interface and the second conductive interface by sensing electrical signals that pass through the first conductive interface due to the second zapping pulses.

5. The system according to claim 1 further comprising a sensor that is configured to monitor a coupling between the first conductive interface and the second conductive interface by sensing test signals that differ from the first zapping pulses and the second zapping pulses.

6. The system according to claim 1 wherein the first conductive interface is coupled to the pulse generation unit via a resistor that is configured to limit a current of the zapping pulses below a predefined current threshold.

7. The system according to claim 1 wherein the first conductive interface is coupled to the pulse generation unit or via a resistive path.

8. The system according to claim 1 further comprising an electrostatic chuck for supporting the wafer; and wherein the first conductive interface and the second conductive interface are configured to pass through holes formed in the electrostatic chuck.

9. The system according to claim 1 wherein the controller is configured to control an intensity of the zapping pulses.

10. The system according to claim 1 wherein the controller is configured to control a duration of the zapping pulses.

11. The system according to claim 1 wherein the controller is configured to control an interval between adjacent zapping pulses.

12. A method for zapping a wafer, the method comprising:
generating, by a pulse generation unit, first zapping pulses and second zapping pulses;
supplying, by a first conductive interface, the first zapping pulses to a first location of a backside insulating layer of a wafer thereby causing a breakdown of the backside insulating layer in the first location;
supplying, by a second conductive interface, the second zapping pulses to a second location of the backside insulating layer of a wafer thereby causing a breakdown of the backside insulating layer in the second location;
monitoring, by a sensor, a coupling between the first conductive interface and the second conductive interface to provide a monitoring result; and
controlling, by a controller, the generating of the first zapping pulses and the second zapping pulses in response to the monitoring result.

13. The method according to claim 12 wherein the controlling of the generating of the first zapping pulses and the second zapping pulses comprises stopping the generation of the first zapping pulses and the second zapping pulses when the monitoring result indicates that there is a breakdown in the first and second locations.

Assignees

• Applied Materials Israel Ltd

Inventors

• Biber Tuvia
• Kerner Efim
• Tov Efraim Siman

Classifications

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10P95/80

  Electrical treatments, e.g. for electroforming · CPC title

• H10P72/0604

  Process monitoring, e.g. flow or thickness monitoring · CPC title

• H10P72/0428

  Apparatus for mechanical treatment or grinding or cutting · CPC title

• H10P72/72

  using electrostatic chucks · CPC title