Multiple MLCC modules

US9805872B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9805872-B2
Application numberUS-201514963766-A
CountryUS
Kind codeB2
Filing dateDec 9, 2015
Priority dateDec 9, 2015
Publication dateOct 31, 2017
Grant dateOct 31, 2017

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An improved module is provided. The module comprises a multiplicity of electronic components wherein each electronic component comprises a first external termination with at least one first longitudinal edge and a second external termination with at least one second longitudinal edge. A first lead is connected to the first longitudinal edge by a first interconnect and a second lead is connected to the second longitudinal edge by a second interconnect.

First claim

Opening claim text (preview).

The invention claimed is: 1. A module comprising: a multiplicity of electronic components wherein each electronic component of said electronic components comprises a first external termination with at least one first longitudinal edge and a second external termination with at least one second longitudinal edge; a first lead connected to each said first longitudinal edge by a first interconnect; a second lead connected to said second longitudinal edge by a second interconnect. 2. The module of claim 1 wherein said first lead is connected to each first longitudinal edge by said first interconnect. 3. The module of claim 1 wherein said first lead is a flat plated lead with at least one said electronic component on each side of said flat plated lead. 4. The module of claim 1 wherein said first lead comprises an offset. 5. The module of claim 4 wherein said offset is selected from laterally offset and horizontally offset. 6. The module of claim 1 wherein said first lead is selected from a round lead frame and a flat lead. 7. The module of claim 6 wherein said first lead comprises at least one flattened region. 8. The module of claim 1 wherein said first lead is selected from a through-hole lead, surface mount lead and a compliant pin lead. 9. The module of claim 8 further comprising a through-hole assembly stand-off feature. 10. The module of claim 1 wherein said first lead comprises a material selected from a ferrous material and a non-ferrous material. 11. The module of claim 1 wherein at least one of said first interconnect or said second interconnect is selected from the group consisting of a transient liquid phase sintering conductive interconnect material, a conductive epoxy, polymer solder and a solder. 12. The module of claim 1 wherein each said electronic component is independently selected from the group consisting of a capacitor, a diode, a resistor, a varistor, an inductor, a fuse and an integrated circuit. 13. The module of claim 11 wherein at least one said electronic component is a capacitor. 14. The module of claim 13 wherein each said electronic component is a capacitor. 15. The module of claim 14 wherein each said capacitor is an MLCC. 16. The module of claim 1 wherein at least two said electronic components have a different size. 17. The module of claim 1 further comprising an encapsulation. 18. The module of claim 1 comprising at least 2 electronic components to no more than 100 electronic components. 19. The module of claim 1 further comprising at least one electronic component in a second row or a second column wherein adjacent longitudinal edges are attached by an interconnect. 20. A method for forming a module comprising: providing a multiplicity of electronic components wherein each electronic component of said electronic components comprises a first external termination with at least one first longitudinal edge and a second external termination with at least on second longitudinal edge; placing a first lead into contact with each said first longitudinal edge with a first interconnect between said first lead and said first longitudinal edge; placing a second lead into contact with said second longitudinal edge with a second interconnect between said second lead and said second longitudinal edge; and heating to form a bond of said first interconnect and said second interconnect. 21. The method for forming a module of claim 20 comprising bonding said first lead to each first longitudinal edge by said first interconnect. 22. The method for forming a module of claim 20 wherein said first lead is a flat plated lead with at least one said electronic component on each side of said flat plated lead. 23. The method for forming a module of claim 20 wherein said first lead comprises an offset. 24. The method for forming a module of claim 23 wherein said offset is selected from laterally offset and horizontally offset. 25. The method for forming a module of claim 20 wherein said first lead is selected from a round lead frame and a flat lead. 26. The method for forming a module of claim 25 wherein said first lead comprises at least one flattened region. 27. The method for forming a module of claim 20 wherein said first lead is selected from a through-hole lead and a surface mount lead. 28. The method for forming a module of claim 27 further comprising a through-hole assembly stand-off feature. 29. The method for forming a module of claim 20 wherein said first lead comprises a material selected from a ferrous material and a non-ferrous material. 30. The method for forming a module of claim 20 wherein at least one of said first interconnect or said second interconnect is selected from the group consisting of a transient liquid phase sintering conductive interconnect material, a conductive epoxy, a polymer solder and a solder. 31. The method for forming a module of claim 20 wherein each said electronic component is independently selected from the group consisting of a capacitor, a diode, a resistor, a varistor, an inductor, a fuse and an integrated circuit. 32. The method for forming a module of claim 31 wherein at least one said electronic component is a capacitor. 33. The method for forming a module of claim 32 wherein each said electronic component is a capacitor. 34. The method for forming a module of claim 33 wherein each said capacitor is an MLCC. 35. The method for forming a module of claim 20 wherein at least two said electronic components have a different size. 36. The method for forming a module of claim 20 further comprising forming an encapsulation. 37. The method for forming a module of claim 20 comprising at least 2 electronic components to no more than 100 electronic components. 38. The method for forming a module of claim 20 further comprising placing at least one electronic component in a second row or a second column with an interconnect between adjacent longitudinal edges and forming a bond of said interconnect.

Assignees

Inventors

Classifications

  • Housing; Encapsulation · CPC title

  • Terminals · CPC title

  • Stacked capacitors (H01G4/33 takes precedence) · CPC title

  • H01G4/38Primary

    Multiple capacitors, i.e. structural combinations of fixed capacitors · CPC title

  • Fixing the capacitor in a housing · CPC title

Patent family

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Frequently asked questions

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What does patent US9805872B2 cover?
An improved module is provided. The module comprises a multiplicity of electronic components wherein each electronic component comprises a first external termination with at least one first longitudinal edge and a second external termination with at least one second longitudinal edge. A first lead is connected to the first longitudinal edge by a first interconnect and a second lead is connected…
Who is the assignee on this patent?
Kemet Electronics Corp
What technology area does this patent fall under?
Primary CPC classification H01G4/38. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 31 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).