Interface module

Patent metadata

Field	Value
Publication number	US-9804982-B2
Application number	US-201514978046-A
Country	US
Kind code	B2
Filing date	Dec 22, 2015
Priority date	Dec 22, 2014
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

An interface module has at least a configuration connection, a reset connection, a transmission connection and a reception connection. The interface module also has at least a first interface processing unit and a second interface processing unit which differs from the first interface processing unit and the connections of which can be connected to the connections of the interface module via a multiplexer. Only one set of interface connections needs to be provided on the interface module. The multiplexer is controlled by a level at the

First claim

The invention claimed is:

1. An interface module, comprising:
a plurality of connections, including a configuration connection, a reset connection, a transmission connection, and a reception connection;
a plurality of interface processing units, including a first interface processing unit and a second interface processing unit different from said first interface processing unit, said interface processing units having a first and a second activation connection, a first and a second transmission connection, and a first and a second reception connection;
a multiplexer having:
a transmission input and a reception input connected to said transmission connection and to said reception connection of said plurality of connections;
a first and a second transmission output and a first and a second reception output, and a control input;
said first transmission output and said first reception output of said multiplexer being connected to said first transmission connection and to said first reception connection of said first interface processing unit; and
said second transmission output and said second reception output of said multiplexer being connected to said second transmission connection and to said second reception connection of said second interface processing unit;

an evaluation circuit having an input connection connected to said configuration connection of said plurality of connections and configured to convert a level of a signal at said input connection into a binary code and to make the signal available at an output connection connected to said control input of said multiplexer;
a selection circuit having a control connection connected to said output connection of said evaluation circuit and having a first and a second signal output connected to said first activation connection of said first interface processing unit and to said second activation connection of said second interface processing unit.

2. The interface module according to claim 1 , wherein said evaluation circuit has a memory unit for storing binary code.

3. The interface module according to claim 2 , wherein:
said configuration connection is a module selection connection;
said evaluation circuit and said selection circuit are implemented by a D-type flip-flop;
said data input connection is connected to said module selection connection, said data output connection is connected to said control input of said multiplexer, and a clock input is connected to said reset connection of the interface module;
said multiplexer further includes a first and a second selection output connection and a third input connection at a predefined potential, said first and second selection output connections being connected to said first activation connection of said first interface processing unit and to said second activation connection of said second interface processing unit.

4. The interface module according to claim 3 , wherein said first activation connection of said first interface processing unit and said second activation connection of said second interface processing unit are connected to a high supply potential of the interface module via a resistor, and the predefined potential present at said third input connection of said multiplexer is low supply potential.

5. The interface module according to claim 2 , wherein:
said configuration connection is a module selection connection;
said evaluation circuit and said selection circuit are implemented by a D-type flip-flop;
said data input connection is connected to said module selection connection, said data output connection is connected to said control input of said multiplexer, and clock input is connected to said reset connection of the interface module;
said data output connection is connected to said first activation connection of said first interface processing unit via an inverter and is connected to said second activation connection of said second interface processing unit or to said first activation connection of said first interface processing unit and is connected to said second activation connection of said second interface processing unit via an inverter.

6. The interface module according to claim 2 , wherein:
said configuration connection is a module selection connection;
said evaluation circuit is connected to said reset connection and includes an A/D converter for converting a level of a signal at said configuration connection into a binary code using an edge of the signal at said reset connection that concludes a reset operation.

7. The interface module according to claim 1 , further comprising a clock signal connection, and wherein:
at least one of said interface processing units has a clock signal input;
said multiplexer additionally has a clock signal input and at least one clock signal output connected to a clock signal input of said interface processing unit.

Assignees

• Continental Automotive Gmbh

Inventors

• Schneider Klaus-Dieter
• Hauck Bernhard

Classifications

• G06F3/00

  Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• G06F13/372 Primary

  using a time-dependent priority, e.g. individually loaded time counters or time slot · CPC title

• G06F13/00

  Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (interface circuits for specific input/output devices G06F3/00 {; multiprogram control therefor  G06F9/46}; multiprocessor systems  G06F15/16 ) · CPC title