Branching to alternate code based on runahead determination

Patent metadata

Field	Value
Publication number	US-9804854-B2
Application number	US-201715444171-A
Country	US
Kind code	B2
Filing date	Feb 27, 2017
Priority date	Jul 18, 2013
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

The description covers a system and method for operating a micro-processing system having a runahead mode of operation. In one implementation, the method includes providing, for a first portion of code, a runahead correlate. When the first portion of code is encountered by the micro-processing system, a determination is made as to whether the system is operating in the runahead mode. If so, the system branches to the runahead correlate, which is specifically configured to identify and resolve latency events likely to occur when the first portion of code is encountered outside of runahead. Branching out of the first portion of code may also be performed based on a determination that a register is poisoned.

First claim

The invention claimed is:

1. A method of operating a microprocessor having a runahead mode, comprising:
storing a runahead code portion that correlates to a portion of code that is executable by the microprocessor;
responsive to encountering the portion of code at run-time, determining if the microprocessor is operating in a runahead mode; and
responsive to the determining, branching to the runahead code portion if the microprocessor is operating in the runahead mode.

2. The method of claim 1 , wherein the branching comprises:
determining whether a register is poisoned; and
branching to the runahead code portion if the microprocessor is operating in the runahead mode and the register is poisoned.

3. The method of claim 1 , wherein the runahead code portion is configured to identify and resolve any latency events which occur when the portion of code is executed outside of the runahead mode.

4. The method of claim 3 , wherein the latency events are selected from a group consisting of: a load miss, a store miss, a branch mispredict and a TLB miss.

5. The method of claim 1 , wherein the runahead code portion is generated based on a dynamic profiling of the portion of code at runtime.

6. The method of claim 1 , wherein the runahead code portion is an alternate version of the portion of code which omits one or more instructions in the portion of code.

7. The method of claim 1 , wherein the runahead code portion is an alternate version of the portion of code that prioritizes memory operations in the portion of code.

8. The method of claim 1 , wherein the runahead code portion comprises an instruction to terminate operation in runahead mode, and wherein the branching to the runahead code portion causes the microprocessor to exit runahead.

9. A method of operating a microprocessor having a runahead mode comprising:
encountering an instruction within a processing pipeline of the microprocessor;
executing and generating output of a condition-testing instruction operable to test whether the microprocessor is operating in the runahead mode when the instruction is encountered and whether the instruction uses a poisoned register; and
branching out of a portion of code containing the instruction based on an output of the condition-testing instruction.

10. The method of claim 9 , where the condition-testing instruction is selectively operable to disable the poison test wherein the branching out of the portion of code containing the instruction occurs if the runahead test is affirmative without regard for the poison test.

11. The method of claim 9 , where the condition-testing instruction is selectively operable to disable the runahead test wherein the branching out of the portion of code containing the instruction occurs if the poison test is affirmative without regard for the runahead test.

12. The method of claim 9 , where the condition-testing instruction is selectively operable to enable both the runahead test and the poison test, such that the branching out of the portion of code containing the instruction occurs if both the runahead test and the poison test are affirmative.

13. The method of claim 9 , further comprising providing a runahead code portion that correlates to the portion of code that is executable by the microprocessor and branching to the runahead code portion when the runahead test is affirmative.

14. The method of claim 13 , wherein the runahead code portion is an alternate version that omits instructions of the portion of code and that is configured to identify and resolve latency events which may occur when the portion of code is executed outside of runahead.

15. The method of claim 13 , wherein the runahead code portion is generated based on a dynamic profiling of the portion of code.

16. The method of claim 13 , wherein the runahead code portion comprises an instruction to terminate operation in runahead mode, such that the branching to the runahead code portion causes the microprocessor to exit runahead.

17. A microprocessor having a runahead mode, comprising:
a memory;
a processing pipeline configured to retrieve instructions and data from the memory;
runahead logic operatively coupled with the processing pipeline and operable to cause the microprocessor to enter the runahead mode upon occurrence of a stall condition in the processing pipeline; and
a portion of code contained in the memory and executable by the processing pipeline, wherein the processing pipeline is configured, in response to encountering the portion of code, to determine whether the microprocessor is in the runahead mode and, responsive to an affirmative determination, to branch to and execute a runahead code portion that correlates to the portion of code in lieu of executing the portion of code, the runahead code portion being configured to identify and resolve latency events which may occur when the portion of code is executed outside of runahead.

18. The microprocessor of claim 17 , wherein the runahead code portion is an alternate version of the portion of code which omits one or more instructions in the portion of code.

19. The microprocessor of claim 17 , wherein the runahead code portion is an alternate version of the portion of code that prioritizes memory operations in the portion of code.

20. The microprocessor of claim 17 , wherein the runahead code portion comprises an instruction to terminate operation in runahead mode, and wherein the branching to the runahead code portion causes the micro-processing system to exit runahead.

Assignees

• Nvidia Corp

Inventors

• Kumar Rohit
• Rozas Guillermo
• Ekman Magnus
• Spracklen Lawrence

Classifications

• G06F9/3865

  using deferred exception handling, e.g. exception flags · CPC title

• G06F9/383 Primary

  Operand prefetching (cache prefetching G06F12/0862) · CPC title

• G06F9/3842

  Speculative instruction execution · CPC title

• G06F9/3867

  using instruction pipelines · CPC title

• G06F9/30189

  according to execution mode, e.g. mode flag · CPC title