Method of operating memory controller and semiconductor storage device including memory controller

Patent metadata

Field	Value
Publication number	US-9804790-B2
Application number	US-201514959089-A
Country	US
Kind code	B2
Filing date	Dec 4, 2015
Priority date	Jan 28, 2015
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

Semiconductor storage devices and methods of operating the same are provided. The semiconductor storage device including a non-volatile memory device, and a memory controller configured to control the non-volatile memory device, the memory controller including a performance control module, the performance control module configured to control a performance level of the memory controller based on state information of the memory controller may be provided.

First claim

What is claimed is:

1. A semiconductor storage device comprising:
a non-volatile memory device; and
a memory controller configured to control the non-volatile memory device, the memory controller including a performance control module, the performance control module configured to control a performance level of the memory controller based on state information of the memory controller, the state information including lifetime information of the memory controller and performance information of the memory controller.

2. The semiconductor storage device of claim 1 , wherein the performance information includes an initial performance level of the memory controller before performing any operations, and the lifetime information includes at least one of an initial lifetime, a reduced lifetime, and a residual lifetime of the memory controller.

3. The semiconductor storage device of claim 1 , further comprising:
a timer configured to count an operation execution time of the memory controller and store the time as a using time information of the memory controller,
wherein when a using time included in the using time information is equal to or greater than a reference using time included in reference using time information and a lifetime included in the lifetime information is equal to or less than a reference lifetime included in reference lifetime information, the performance control module is configured to set a limited performance level of the memory controller based on the lifetime information and the using time information, and control the performance level of the memory controller so as to be equal to or less than the limited performance level.

4. The semiconductor storage device of claim 3 , wherein the memory controller further includes a clock signal generator, and the clock signal generator is configured to generate a clock signal having a frequency that varies according to an input voltage, and
wherein when the limited performance level of the memory controller is set, the performance control module is configured to control the performance level of the memory controller so as to be equal or less than the limited performance level by limiting the input voltage supplied to the clock signal generator.

5. The semiconductor storage device of claim 4 , wherein the performance control module is configured to determine whether to control the performance level of the memory controller based on an operating state of the memory controller.

6. The semiconductor storage device of claim 5 , wherein the performance control module is further configured to,
increase the input voltage when an improvement of the performance level of the memory controller is desired, and
decrease or maintain the input voltage when the improvement of the performance level of the memory controller is not desired.

7. The semiconductor storage device of claim 1 , wherein the memory controller further includes a lifetime information calculator, and the lifetime information calculator is configured to update the lifetime information with new lifetime information.

8. The semiconductor storage device of claim 1 , wherein the performance level of the memory controller corresponds to at least one of a number of commands processed by the memory controller per unit time, an amount of data written by the memory controller per unit time, and an amount of data read by the memory controller per unit time.

9. The semiconductor storage device of claim 1 , further comprising:
an information buffer configured to store the state information.

10. The semiconductor storage device of claim 1 , wherein the semiconductor storage device is a solid state drive (SSD) or a secure digital (SD) card.

11. A method of operating a memory controller for controlling a non-volatile memory device, the method comprising:
receiving an operation command from a host;
determining whether to limit a performance level of the memory controller based on lifetime information of the memory controller, the determining including,
determining whether a using time included in using time information generated by counting an operation execution time of the memory controller is equal to or greater than a reference using time included in reference using time information, and
determining whether a lifetime included in the lifetime information is equal to or less than a reference lifetime included in reference lifetime information;

controlling the performance level of the memory controller based on a result of the determining; and
performing an operation corresponding to the operation command at the performance level.

12. The method of claim 11 , wherein the controlling comprises:
setting a limited performance level of the memory controller when the using time is equal to or greater than the reference using time and the lifetime is equal to or less than the reference lifetime; and
adjusting the performance level of the memory controller so as to be equal to or less than the limited performance level.

13. The method of claim 11 , further comprising:
determining whether an adjustment of the performance level of the memory controller is desired based on an operating state of the memory controller,
wherein the controlling the performance level of the memory controller includes,
improving the performance level of the memory controller based on at least one of the lifetime information of the memory controller and performance information of the memory controller, if it is determined that the improvement of the performance level of the memory controller is desired; and
maintaining or lowering the performance level of the memory controller if it is determined that the improvement of the performance level of the memory controller is not desired.

14. A semiconductor storage device comprising:
a non-volatile memory device; and
a memory controller configured to control the non-volatile memory device according to a command from a host, the memory controller including,
a host interface configured to exchange at least one of commands and data with a host,
an information buffer configured to store state information, the state information including lifetime information of the memory controller and performance information of the memory controller, and
a processor configured to receive the state information from the information buffer and control a performance level of the memory controller based on the state information thereof and an expected using time thereof.

15. The semiconductor storage device of claim 14 , wherein the memory controller further includes a central processing unit (CPU), the CPU is configured to execute a data read or a data write operation to or from the non-volatile memory device, and the processor is further configured to set a performance level of the CPU as a performance level of the memory controller.

16. The semiconductor storage device of claim 15 , wherein the memory controller further includes a clock signal generator, the clock signal generator is configured to generate a clock signal having a frequency varying according to an input voltage, and the processor is further configured to control the performance level of the CPU by adjusting a clock frequency applied to the CPU based on a state information of the CPU and an expected using time of the CPU.

17. The semiconductor storage device of claim 14 , wherein the performance information includes the performance level after completing an immediate previous operation, and the lifetime information includes at least one of an initial lifetime, a reduced lifetime, and a residual lifetim

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Jun-Bum
• Shim Ho-Jun

Classifications

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0655

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title

• G06F3/0616 Primary

  in relation to life time, e.g. increasing Mean Time Between Failures [MTBF] · CPC title