Embedded speaker protection for automotive audio power amplifier

Patent metadata

Field	Value
Publication number	US-9800221-B2
Application number	US-201615356269-A
Country	US
Kind code	B2
Filing date	Nov 18, 2016
Priority date	Dec 30, 2011
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

A circuit can be used in a speaker system. The circuit includes an amplifier with an output configured to be coupled to a speaker. An offset comparator has an input coupled the output of the amplifier and is configured to provide an offset control signal. A digital circuit has a first input coupled to an output of the offset comparator, a second input configured to receive an amplifier control signal, a third input configured to receive a play control signal, and an output configured to provide a forced mute signal that can be used to control the amplifier.

First claim

What is claimed is:

1. A circuit comprising:
an amplifier with an output configured to be coupled to a speaker;
an offset comparator with an input coupled to the output of the amplifier, the offset comparator configured to provide an offset control signal; and
a digital circuit having a first input coupled to an output of the offset comparator, a second input configured to receive an amplifier control signal, a third input configured to receive a play control signal, and an output configured to provide a forced mute signal for controlling the amplifier.

2. The circuit of claim 1 , wherein the digital circuit is embedded in the amplifier.

3. The circuit of claim 1 , wherein the digital circuit comprises:
an intermediate node for providing a speaker protection control signal;
a first latch coupled to the first input coupled to receive the offset control signal;
a first logic gate coupled to the input coupled to receive the play control signal, the first logic gate also coupled to receive the offset control signal and the speaker protection control signal;
a second logic gate coupled to the first latch to receive the play control signal and the speaker protection control signal;
a second latch coupled to the first logic gate to provide the forced mute signal; and
a third latch coupled to the second logic gate and to the intermediate node.

4. The circuit of claim 3 , wherein the first, second, and third latches are each controlled by a common amplifier control signal.

5. The circuit of claim 3 , wherein the first, second, and third latches each comprise a D-type flip flops.

6. The circuit of claim 5 , wherein each D-type flip flop comprises an inverted output coupled to a D input.

7. The circuit of claim 3 , wherein the first logic gate and the second logic gate each comprise a three-input NAND gate.

8. The circuit of claim 3 , wherein the first logic gate and the second logic gate each comprise a three-input AND gate.

9. The circuit of claim 1 , wherein the first input comprises an offset indication input node, the second input comprises a mute control output node and the third input comprises a play control signal input node, and wherein the digital circuit comprises:
an intermediate node configured to carry a speaker protection control signal;
a first latch with an input coupled to the offset indication input node;
a first comparison circuit with an output coupled to the mute control output node, the first comparison circuit having inputs coupled to the play control signal input node, the offset indication input node, and the intermediate node; and
a second comparison circuit with an output coupled to the intermediate node, the second comparison circuit having inputs coupled to the play control signal input node, an output of the first latch, and the intermediate node.

10. The circuit of claim 9 , wherein the first comparison circuit comprises a first logic gate and wherein the second comparison circuit comprises a second logic gate.

11. The circuit of claim 10 , wherein the first comparison circuit further comprises a second latch coupled to an output of the first logic gate and wherein the second comparison circuit further comprises a third latch coupled to an output of the second logic gate.

12. The circuit of claim 11 , wherein the first, second, and third latches are each controlled by a common amplifier control signal.

13. The circuit of claim 11 , wherein the first, second, and third latches each comprise a D-type flip flop that comprises an inverted output coupled to a D input.

14. The circuit of claim 10 , wherein the first logic gate and the second logic gate each comprise a three-input NAND gate.

15. A circuit comprising:
an amplifier with an output configured to be coupled to a speaker;
an offset comparator with an input coupled the output of the amplifier to the speaker, the offset comparator configured to provide an offset control signal;
means for generating a speaker control signal based upon a play control signal and an earlier value of the offset control signal; and
means for generating a force mute signal based on the offset control signal, the play control signal and the generated speaker control signal.

16. A speaker system comprising:
a speaker;
an amplifier with an output coupled to the speaker, the amplifier including a digital circuit embedded therein, the digital circuit comprising having a first input, a second input configured to receive an amplifier control signal, a third input configured to receive a play control signal, and an output configured to provide a forced mute signal;
an offset comparator with an input coupled the output of the amplifier and an output coupled to the first input of the digital circuit embedded in the amplifier, the offset comparator configured to provide an offset control signal; and
a microprocessor coupled to the digital circuit embedded in the amplifier to receive the forced mute signal for controlling the amplifier.

17. The system of claim 16 , wherein the digital circuit embedded in the amplifier comprises:
an intermediate node for providing a speaker protection control signal;
a first latch coupled to the first input coupled to receive the offset control signal;
a first logic gate coupled to the input coupled to receive the play control signal, the first logic gate also coupled to receive the offset control signal and the speaker protection control signal;
a second logic gate coupled to the first latch to receive the play control signal and the speaker protection control signal;
a second latch coupled to the first logic gate to provide the forced mute signal; and
a third latch coupled to the second logic gate and to the intermediate node.

18. The system of claim 17 , wherein the first, second, and third latches each comprise a D-type flip flops that comprises an inverted output coupled to a D input, and wherein the first logic gate and the second logic gate each comprise a three-input AND gate.

19. The system of claim 16 , wherein the first input comprises an offset indication input node, the second input comprises a mute control output node and the third input comprises a play control signal input node, and wherein the digital circuit comprises:
an intermediate node configured to carry a speaker protection control signal;
a first latch with an input coupled to the offset indication input node;
a first comparison circuit with an output coupled to the mute control output node, the first comparison circuit having inputs coupled to the play control signal input node, the offset indication input node, and the intermediate node; and
a second comparison circuit with an output coupled to the intermediate node, the second comparison circuit having inputs coupled to the play control signal input node, an output of the first latch, and the intermediate node.

20. The system of claim 19 , wherein the first comparison circuit comprises a first logic gate and a second latch coupled to an output of the first logic gate;
wherein the second comparison circuit comprises a second logic gate and a third latch coupled to an output of the second logic gate;
wherein the first, second, and third latches are each controlled by a common amplifier control signal;
wherein the first, second, and third latches each comprise a D-type flip flop; and
wherein the first logic gate and the second logic gate each comprise a three-input NAND gate.

Assignees

• Stmicroelectronics (Shenzhen) R&D Co Ltd
• St Microelectronics Srl
• Stmicroelectronics (Shenzhen) R&D Co Ltd

Inventors

• Li Xiangsheng
• Meroni Cristiano
• Yang Mei
• Xiong Xian Feng

Classifications

• H03F2200/471

  the voltage being sensed · CPC title

• H03F1/52

  Circuit arrangements for protecting such amplifiers {(monitoring arrangements G01R31/28; increasing reliability in communication systems, e.g. using redundancy H04B1/74)} · CPC title

• H04R3/00 Primary

  Circuits for transducers (arrangements for producing a reverberation or echo sound G10K15/08; amplifiers H03F) · CPC title

• H03G3/348 Primary

  Muting in response to a mechanical action or to power supply variations, e.g. during tuning; Click removal circuits · CPC title

• H03F2200/78

  A comparator being used in a controlling circuit of an amplifier · CPC title