Formation of a bottom source-drain for vertical field-effect transistors

Patent metadata

Field	Value
Publication number	US-9799765-B1
Application number	US-201615196375-A
Country	US
Kind code	B1
Filing date	Jun 29, 2016
Priority date	Jun 29, 2016
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

In an embodiment, this invention relates to a vertical field-effect transistor component including a bottom source-drain layer and a method of creating the same. The method of forming a bottom source-drain layer of a vertical field-effect transistor component can comprise forming an anchor structure on a substrate. A sacrificial layer can be deposited on a middle region of the substrate and a channel layer can be deposited on the sacrificial layer. A plurality of vertical fins can be formed on the substrate and the sacrificial layer can be removed such that the plurality of vertical fins in the middle region form a plurality of floating fins having a gap located between the plurality of floating fins and the substrate. The bottom source-drain layer can then be formed such that the bottom source-drain layer fills in the gap.

First claim

What is claimed is:

1. A method of forming a bottom source-drain layer of a vertical field-effect transistor component, the method comprising:
forming an anchor structure on a substrate such that the substrate comprises a first anchor region, a second anchor region, and a middle region located there between;
depositing a sacrificial layer on the middle region of the substrate;
depositing a channel layer on the sacrificial layer such that a surface of the channel layer is coplanar with a surface of the anchor structure;
forming a plurality of vertical fins on the substrate;
removing the sacrificial layer such that the plurality of vertical fins in the middle region form a plurality of floating fins having a gap located between the plurality of floating fins and the substrate; and
depositing the bottom source-drain layer such that the bottom source-drain layer fills in the gap.

2. The method of claim 1 , wherein the gap has a height of 20 to 40 nanometers.

3. The method of claim 1 , wherein a thickness of the bottom source-drain layer located in a non-fin region is 10 to 20 nanometers.

4. The method of claim 3 , wherein the thickness of the bottom source-drain layer located in the non-fin region varies by less than or equal to 2 nanometers.

5. The method of claim 1 , wherein the forming the plurality of vertical fin comprises etching into the sacrificial layer; wherein an etch depth into the sacrificial layer varies depending on a pitch of vertical fins.

6. The method of claim 1 , further comprising depositing an oxide liner on the plurality of vertical fins and performing a linear etch back step of the oxide liner prior to removing the sacrificial layer.

7. The method of claim 1 , wherein the patterning the plurality of vertical fins comprises using a sidewall image transfer technique.

8. The method of claim 7 , wherein the sidewall image transfer technique comprises forming a patterned mandrel layer on the fin layer; depositing a sidewall spacer layer on the patterned mandrel layer and the fin layer; and removing a top facing sidewall spacer layer and the patterned mandrel layer.

9. A method of forming a bottom source-drain layer of a vertical field-effect transistor component, the method comprising:
forming an anchor structure on a substrate such that the substrate comprises a first anchor region, a second anchor region, and a middle region located there between;
depositing a sacrificial layer on the middle region of the substrate;
depositing a channel layer on the sacrificial layer such that a surface of the channel layer is coplanar with a surface of the anchor structure;
depositing a fin layer on the channel layer and on the anchor structure;
forming a patterned mandrel layer on the fin layer;
depositing a sidewall spacer layer on the patterned mandrel layer and the fin layer;
forming a plurality of vertical fins from the sidewall spacer layer; wherein the plurality of vertical fins comprise the sidewall spacer layer, the fin layer, and the channel layer; wherein the plurality of vertical fins span the middle region from the first anchor region to the second anchor region; wherein the forming exposes the sacrificial layer;
depositing an oxide liner and performing a liner etch back of the oxide liner;
removing the sacrificial layer such that the plurality of vertical fins in the middle region form a plurality of floating fins having a gap located between the plurality of floating fins and the substrate; and
depositing the bottom source-drain layer such that the bottom source-drain layer fills in the gap.

10. The method of claim 9 , wherein the gap has a height of 20 to 40 nanometers.

11. The method of claim 9 , wherein a thickness of the bottom source-drain layer located in a non-fin region is 10 to 50 nanometers.

12. The method of claim 11 , wherein a thickness of the bottom source-drain layer located in the non-fin region varies by less than or equal to 2 nanometers.

13. The method of claim 9 , wherein the channel layer comprises silicon and the sacrificial layer comprises silicon germanium.

14. The method of claim 9 , wherein the anchor structure has an anchor structure height of 30 to 100 nanometers.

Assignees

• IBM

Inventors

• Bergendahl Marc A
• Cheng Kangguo
• Lie Fee Li
• Mochizuki Shogo
• Wang Junli

Classifications

• H01L29/41791

  Electricity · mapped topic

• H01L29/7827 Primary

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic

• H01L29/785

  Electricity · mapped topic