Semiconductor devices including field effect transistors

Patent metadata

Field	Value
Publication number	US-9799674-B2
Application number	US-201615050607-A
Country	US
Kind code	B2
Filing date	Feb 23, 2016
Priority date	Mar 27, 2015
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

A semiconductor device includes a first device isolation layer defining active regions spaced apart from each other along a first direction on a substrate, second device isolation layers defining a plurality of active patterns protruding from the substrate, the second device isolation layers extending in the first direction to be spaced apart from each other in a second direction and connected to the first device isolation layer, a gate structure extending in the second direction on the first device isolation layer between the active regions, a top surface of the second device isolation layer being lower than a top surface of the active pattern, a top surface of the first device isolation layer being higher than the top surface of the active pattern, and at least part of a bottom surface of the gate structure being higher than the top surface of the active pattern.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first device isolation layer between active regions spaced apart from each other in a first direction on a substrate;
second device isolation layers between active patterns protruding from the substrate in each active region, the second device isolation layers extending in the first direction and being spaced apart from each other in a second direction crossing the first direction, and each of the second device isolation layers being connected to the first device isolation layer; and
a gate structure extending in the second direction and penetrating the first device isolation layer between the active regions,
wherein at least a part of a bottom surface of the gate structure contacts a bottom surface of the first device isolation layer.

2. The semiconductor device as claimed in claim 1 , further comprising a first logic cell and a second logic cell adjacent to each other in the second direction,
wherein the first device isolation layer is between the active regions in the first logic cell, and
wherein the gate structure extends in the second direction to cross at least one active pattern of the second logic cell.

3. The semiconductor device as claimed in claim 1 , wherein a first part of the bottom surface of the gate structure contacts end portions of the active patterns spaced apart from each other in the second direction, and a second part of the bottom surface of the gate structure contacts the bottom surface of the first device isolation layer.

4. The semiconductor device as claimed in claim 1 , wherein the gate structure is spaced apart from the active patterns, and the bottom surface of the gate structure contacts the bottom surface of the first device isolation layer.

5. The semiconductor device as claimed in claim 1 , wherein a top surface of the gate structure is at a higher level than topmost surfaces of the active patterns.

6. The semiconductor device as claimed in claim 5 , wherein a top surface of the second device isolation layer is at a lower level than the topmost surfaces of the active patterns.

7. The semiconductor device as claimed in claim 1 , wherein the gate structure includes a gate electrode extending in the second direction and a gate insulating pattern extending along a bottom surface of the gate electrode, the gate electrode including a conductive material.

8. The semiconductor device as claimed in claim 7 , wherein at least a part of a bottommost surface of the gate insulating pattern contacts the bottom surface of the first device isolation layer.

9. The semiconductor device as claimed in claim 1 , wherein the gate structure is a first gate structure, and
further comprising second gate structures extending in the second direction on the active regions, each of the second gate structures crossing the active patterns spaced apart from each other.

10. The semiconductor device as claimed in claim 9 , further comprising source/drain regions in the active patterns at opposite sides of each of the second gate structures, the first gate structure being electrically insulated from adjacent source/drain regions by the first device isolation layer.

11. A semiconductor device, comprising:
a first device isolation layer between active regions spaced apart from each other along a first direction on a substrate;
second device isolation layers between a plurality of active patterns protruding from the substrate in each active region, the second device isolation layers extending in the first direction and being spaced apart from each other in a second direction crossing the first direction, and each of the second device isolation layers connected to the first device isolation layer; and
a gate structure extending in the second direction on the first device isolation layer between the active regions,
wherein a top surface of the second device isolation layer is at a lower level than a topmost surface of the active pattern, and a top surface of the first device isolation layer is at a higher level than the topmost surface of the active pattern, and
wherein at least a part of a bottom surface of the gate structure is at a higher level than the topmost surface of the active pattern.

12. The semiconductor device as claimed in claim 11 , wherein a first part of the bottom surface of the gate structure contacts end portions of the active patterns spaced apart from each other in the second direction, and a second part of the bottom surface of the gate structure contacts the top surface of the first device isolation layer.

13. The semiconductor device as claimed in claim 11 , wherein the gate structure is spaced apart from the active patterns along the first direction to have a non-overlapping relationship with the active patterns, and the bottom surface of the gate structure contacts the top surface of the first device isolation layer.

14. The semiconductor device as claimed in claim 11 , wherein at least the part of the bottom surface of the gate structure contacts the top surface of the first device isolation layer.

15. The semiconductor device as claimed in claim 11 , wherein:
the gate structure includes a gate electrode extending in the second direction and a gate insulating pattern extending along a bottom surface of the gate electrode, and
the gate electrode includes a conductive material, at least a portion of the first device isolation layer extending between and to a higher height than two adjacent active patterns of two different active regions, respectively, and in contact with the gate structure.

16. The semiconductor device as claimed in claim 15 , wherein at least a part of a bottom surface of the gate insulating pattern contacts the top surface of the first device isolation layer.

17. The semiconductor device as claimed in claim 11 , wherein the gate structure is a first gate structure, and
further comprising second gate structures extending in the second direction on the active regions, the second gate structures crossing the active patterns and being spaced apart from each other.

18. The semiconductor device as claimed in claim 17 , further comprising source/drain regions in the active patterns at opposite sides of each of the second gate structures, the first gate structure being electrically insulated from adjacent source/drain regions by the first device isolation layer.

19. The semiconductor device as claimed in claim 11 , further comprising a first logic cell and a second logic cell adjacent to each other in the second direction,
wherein the first device isolation layer is between the active regions in the first logic cell, and
wherein the gate structure extends in the second direction to cross at least one active pattern of the second logic cell.

20. The semiconductor device as claimed in claim 19 , further comprising source/drain region in a first part of the at least one active pattern of the second logic cell at opposite sides of the gate structure,
wherein a second part of the at least one active pattern under the gate structure in the second logic cell is a channel region.

21. A semiconductor device, comprising:
a first device isolation layer extending in a second direction and defining active regions spaced apart from each other along a first direction on a substrate;
second device isolation layers defining a plurality of active patterns protruding from the substrate in each active region, the second device isolation layers extending in the first direction to be spaced apart from each o

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yoon Changseop
• You Junggun
• Park Youngjoon
• LEE Jeonghyo

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H01L21/76224

  Electricity · mapped topic

• H01L29/42376

  Electricity · mapped topic

• H01L29/66659

  Electricity · mapped topic