Semiconductor device including different orientations of memory cell array and peripheral circuit transistors

Patent metadata

Field	Value
Publication number	US-9484354-B2
Application number	US-201514637538-A
Country	US
Kind code	B2
Filing date	Mar 4, 2015
Priority date	Jun 3, 2014
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

A memory device includes a memory cell on a first region of a substrate. An active region is in a second region neighboring the first region of the substrate, and an extension direction of the active region has an acute angle with the <110> direction of the substrate. A transistor serving as a peripheral circuit is on the second region of the substrate. In the memory device, defects or failures due to a crystal defects or a dislocation of the substrate may decrease.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate comprising a <110> direction;
a memory cell on a first region of the substrate, wherein the memory cell includes a channel structure extending in a direction substantially perpendicular to a top surface of the substrate;
an active region in a second region neighboring the first region of the substrate, an extension direction of the active region having an acute angle with the <110> direction of the substrate; and
a transistor serving as a peripheral circuit on the second region of the substrate.

2. The device of claim 1 further comprising:
a dielectric structure on the channel structure; and
a plurality agate lines stacked on the dielectric structure, the plurality of gate lines being spaced apart from each other.

3. The device of claim 2 , wherein the gate lines extend in the <110> direction of the substrate.

4. The device of claim 1 , wherein the extension direction of the active region has an angle of about 10 degrees to about 80 degrees with the <110> direction of the substrate.

5. The device of claim 1 , wherein the substrate is a (100) silicon wafer.

6. The device of claim 1 , further comprising a dummy region adjacent to the first region in the second region, wherein the dummy region includes a dummy active region therein.

7. The device of claim 6 , wherein the dummy active region has a linear shape and extends in a direction substantially parallel to a boundary line of the first region.

8. The device of claim 6 , wherein the dummy active region extends in a direction having an angle of about 10 degrees to about 80 degrees with the <110> direction of the substrate.

9. The device of claim 8 , wherein the dummy active region includes a plurality of dummy active regions regularly arranged in a direction substantially parallel to a boundary line of the first region.

10. The device of claim 1 , wherein the transistor includes a gate electrode and an impurity region, and the gate electrode extends in a direction substantially perpendicular to a longitudinal direction of the active region.

11. The device of claim 1 , wherein the transistor includes a gate electrode and an impurity region, and the gate electrode extends in the <100> direction of the substrate.

12. A semiconductor device, comprising:
a semiconductor substrate comprising a <110> direction;
a memory cell on a first region of the substrate;
an active region in a second region neighboring the first region of the substrate, an extension direction of the active region having an acute angle with the <110> direction of the substrate;
a transistor serving as a peripheral circuit on the second region of the substrate; and
a dummy active region in the second region adjacent to the first region, an extension direction of the dummy active region having an angle of about 10 degrees to about 80 degrees with the <110> direction of the substrate.

13. The device of claim 12 , wherein the extension direction of the active region has an angle of about 10 degrees to about 80 degrees with the <110> direction of the substrate.

14. The device of claim 12 , wherein the active region extends in the <110> direction of the substrate.

15. The device of claim 12 , wherein the transistor includes a gate electrode and an impurity region, and the gate electrode extends in a direction substantially perpendicular to a longitudinal direction of the active region.

16. A semiconductor device, comprising:
a substrate comprising a <110> direction;
a memory cell array comprising a plurality of word lines that extend along the substrate parallel or perpendicular to the <110> direction; and
a plurality of peripheral circuit transistors that extend along the substrate oblique to the <110> direction.

17. The device of claim 16 wherein the plurality of peripheral circuit transistors extend along the substrate at an angle of between about 10 degrees and about 80 degrees to the <110> direction.

18. The device of claim 16 further comprising a plurality of dummy active regions between the memory cell array and the plurality of peripheral cell transistors, the dummy active regions not comprising transistors therein.

19. The device of claim 16 wherein the memory cell array further comprises a plurality of memory cells having channel structures that extend perpendicular to a face of the substrate.

20. The device of claim 16 wherein the substrate comprises monocrystalline silicon and also comprises a <100> direction, and wherein the plurality of peripheral circuit transistors extend along the <100> direction.

Assignees

• Lee Sung-Hun
• Park Jong-Ho
• Lee Joon-Hee
• Lee Hee-Jueng
• Samsung Electronics Co Ltd

Inventors

• Lee Sung-Hun
• Park Jong-Ho
• Lee Joon-Hee
• Lee Hee-Jueng

Classifications

• H10D30/66 Primary

  Vertical DMOS [VDMOS] FETs · CPC title

• H10D62/405

  Orientations of crystalline planes · CPC title

• H01L27/11582

  Electricity · mapped topic

• H01L27/11573 Primary

  Electricity · mapped topic

• H01L29/045

  Electricity · mapped topic