Integrated electronic device with transceiving antenna and magnetic interconnection

Patent metadata

Field	Value
Publication number	US-9799630-B2
Application number	US-201615376485-A
Country	US
Kind code	B2
Filing date	Dec 12, 2016
Priority date	Dec 30, 2008
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

An embodiment of an integrated electronic device having a body, made at least partially of semiconductor material and having a top surface, a bottom surface, and a side surface, and a first antenna, which is integrated in the body and enables magnetic or electromagnetic coupling of the integrated electronic device with a further antenna. The integrated electronic device moreover has a coupling region made of magnetic material, which provides, in use, a communication channel between the first antenna and the further antenna.

First claim

The invention claimed is:

1. A semiconductor structure, comprising:
a semiconductor layer having a top surface and a bottom surface;
an insulating layer mounted to the top surface of the semiconductor layer;
a first winding configured to generate a magnetic flux, said first winding positioned within the insulating layer;
a magnetic region disposed in the semiconductor layer in alignment with the first winding;
a first magnetic core positioned over the insulating layer and aligned with at least part of said first winding; and
a second magnetic core positioned under the bottom surface of the semiconductor layer and aligned with at least a portion of the magnetic region.

2. The semiconductor structure of claim 1 , wherein said magnetic region has a bottom surface coplanar with the bottom surface of the semiconductor layer.

3. The semiconductor structure of claim 1 , wherein said magnetic region has a bottom surface offset from the bottom surface of the semiconductor layer.

4. The semiconductor structure of claim 1 , wherein said magnetic region extends within the insulating layer.

5. The semiconductor structure of claim 4 , wherein the first winding wraps around a portion of the magnetic region that extends within the insulating layer.

6. The semiconductor structure of claim 1 , further comprising a further magnetic region providing a closed magnetic path that passes through the first and second magnetic cores and said magnetic region.

7. The semiconductor structure of claim 6 , wherein said further magnetic region is disposed in the semiconductor layer.

8. The semiconductor structure of claim 6 , wherein said further magnetic region is positioned on a sidewall of the semiconductor layer that extends between the top and bottom surfaces.

9. A semiconductor structure, comprising:
a first semiconductor substrate;
a first winding mounted to the first semiconductor substrate;
a second semiconductor substrate;
a second winding mounted to the second semiconductor substrate;
wherein the first and second semiconductor substrates are mounted one over a top of the other;
a first magnetic region positioned within the first semiconductor substrate to support a mutual inductance between the first and second windings for wireless transmission of signals or power between the first and second windings.

10. The semiconductor structure of claim 9 , wherein the first winding has a first axis and the second winding has a second axis; and wherein the first and second axes pass through the first magnetic region.

11. The semiconductor structure of claim 10 , wherein the first and second axes are aligned.

12. The semiconductor structure of claim 9 , further comprising an adhesive layer for mounting the first and second semiconductor substrates one over the top of the other.

13. The semiconductor structure of claim 9 , wherein the first winding is provided within a first layer including metal lines and the second winding is provided within a second layer including metal lines.

14. The semiconductor structure of claim 13 , wherein the first magnetic region extends into the first layer and is surrounded by the first winding.

15. The semiconductor structure of claim 9 , wherein the first magnetic region has a bottom surface coplanar with a bottom surface of the first semiconductor substrate.

16. The semiconductor structure of claim 9 , further comprising a second magnetic region positioned within the second semiconductor substrate.

17. The semiconductor structure of claim 16 , wherein the first magnetic region has a bottom surface coplanar with a bottom surface of the first semiconductor substrate, the second magnetic region has a bottom surface coplanar with a bottom surface of the second semiconductor substrate, and the first and second semiconductor substrates are mounted one over top of the other with the bottom surfaces of the first and second semiconductor substrates facing each other.

18. The semiconductor structure of claim 17 , further comprising a structure for providing a close magnetic path which passes through the first and second magnetic regions.

19. The semiconductor structure of claim 17 , further comprising a magnetic layer extending between the first and second semiconductor substrates facing each other.

20. The semiconductor structure of claim 9 , wherein the first winding is provided in a first region including metal lines within an insulating material and the second winding is provided in a second region including metal lines within an insulating material.

21. The semiconductor structure of claim 20 , wherein the first magnetic region extends into the first region and is surrounded by the first winding.

22. A semiconductor structure, comprising:
a semiconductor layer having a top surface and a bottom surface;
an insulating layer mounted to the top surface of the semiconductor layer;
a first winding configured to generate a magnetic flux, said first winding positioned within the insulating layer;
a magnetic region disposed in the semiconductor layer in alignment with the first winding;
a first magnetic core positioned over the insulating layer and aligned with at least part of said first winding;
a second magnetic core positioned under the bottom surface of the semiconductor layer and aligned with at least a portion of the magnetic region; and
a plurality of magnetic confinement vias extending into said insulating layer from a bottom surface of the first magnetic core, said confinement vias positioned outside of a periphery of the first winding.

23. The semiconductor structure of claim 22 , wherein said magnetic region has a bottom surface coplanar with the bottom surface of the semiconductor layer.

24. The semiconductor structure of claim 22 , wherein said magnetic region has a bottom surface offset from the bottom surface of the semiconductor layer.

25. The semiconductor structure of claim 22 , wherein said magnetic region extends within the insulating layer.

26. The semiconductor structure of claim 25 , wherein the first winding wraps around a portion of the magnetic region that extends within the insulating layer.

27. The semiconductor structure of claim 22 , further comprising a further magnetic region providing a closed magnetic path that passes through the first and second magnetic cores and said magnetic region.

28. The semiconductor structure of claim 27 , wherein said further magnetic region is disposed in the semiconductor layer.

29. The semiconductor structure of claim 27 , wherein said further magnetic region is positioned on a sidewall of the semiconductor layer that extends between the top and bottom surfaces.

Assignees

• St Microelectronics Srl

Inventors

• Pagani Alberto
• Girlando Giovanni

Classifications

• G01R31/3025

  Wireless interface with the DUT · CPC title

• G01R1/07314

  the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support (on an elastic support, e.g. a film, G01R1/0735) · CPC title

• H01Q1/36

  Structural form of radiating elements, e.g. cone, spiral, umbrella; {Particular materials used therewith}(H01Q1/08, H01Q1/14 take precedence) · CPC title

• H01Q1/2283

  mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package · CPC title

• H01Q7/00

  Loop antennas with a substantially uniform current distribution around the loop and having a directional radiation pattern in a plane perpendicular to the plane of the loop · CPC title