Dual power converter package

Patent metadata

Field	Value
Publication number	US-9799586-B2
Application number	US-201514919653-A
Country	US
Kind code	B2
Filing date	Oct 21, 2015
Priority date	Mar 28, 2012
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

A dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control FET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a first plurality of contacts configured to receive control signals for each of the control FETs and each of the sync FETs from a driver integrated circuit (IC) external to the leadframe. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control FET and the second sync FET via a second clip, respectively.

First claim

The invention claimed is:

1. A dual power converter package comprising:
a leadframe comprising:
a first control FET paddle configured for electrical connection to a drain of a first control FET;
a second control FET paddle configured for electrical connection to a drain of a second control FET;
a sync FET paddle that is continuous, and configured for electrical connection to a source of a first sync FET and a source of a second sync FET, between said source of said first sync FET and said source of said second sync FET;
a first plurality of contacts configured to receive control signals for said first and second control FETs and said first and second sync FETs from a driver integrated circuit (IC) external to said leadframe;
a first switched node configured for electrical connection to a source of said first control FET and a drain of said first sync FET; and

a first inductor and a first capacitor connected between said first switched node and ground.

2. The dual power converter package of claim 1 , further comprising a second switched node configured for electrical connection to a source of said second control FET and a drain of said second sync FET.

3. The dual power converter package of claim 2 , further comprising a second inductor and a second capacitor connected between said second switched node and ground.

4. The dual power converter package of claim 2 , wherein said leadframe further comprises a second output voltage contact configured to provide a second output voltage from said second switched node.

5. The dual power converter package of claim 2 , wherein said second switched node is coupled to said source of said second control FET and said drain of said second sync FET via a first trace, connector, clip, ribbon, or wire.

6. The dual power converter package of claim 1 , wherein said first control PET paddle and said second control PET paddle are disposed substantially symmetrically on said leadframe.

7. The dual power converter package of claim 1 , wherein said leadframe further comprises a first supply voltage contact configured for externally receiving a first supply voltage.

8. The dual power converter package of claim 7 , wherein said leadframe further comprises a second supply voltage contact configured for externally receiving a second supply voltage.

9. The dual power converter package of claim 1 , wherein said leadframe further comprises a ground contact for externally receiving a ground connection.

10. The dual power converter package of claim 1 , wherein said leadframe further comprises a first output voltage contact configured to provide a first output voltage from said first switched node.

11. The dual power converter package of claim 1 , wherein said first switched node is coupled to said source of said first control FET and said drain of said first sync FET via a first trace, connector, clip, ribbon, or wire.

12. A dual power converter package comprising:
a leadframe comprising:
a first control FET disposed on a first control FET paddle;
a second control FET disposed on a second control FET paddle;
a first sync FET and a second sync FET, each disposed on a sync FET paddle that is continuous, and that is configured for electrical connection to a source of said first sync FET and a source of said second sync FET, between said source of said first sync FET and said source of said second sync FET;
a first plurality of contacts configured to receive control signals for said first and second control FETs and said first and second sync FETs from a driver integrated circuit (IC) external to said leadframe;
a first switched node configured for electrical connection to a source of said first control FET and a drain of said first sync FET; and

a first inductor and a first capacitor connected between said first switched node and ground.

13. The dual power converter package of claim 12 , wherein said leadframe further comprises a second switched node configured for electrical connection to a source of said second control FET and a drain of said second sync FET.

14. The dual power converter package of claim 13 , wherein said leadframe further comprises:
a first output voltage contact configured to provide a first output voltage from said first switched node;
a second output voltage contact configured to provide a second output voltage from said second switched node.

15. The dual power converter package of claim 13 , further comprising:
a second inductor and a second capacitor connected between said second switched node and ground.

16. The dual power converter package of claim 12 , wherein:
said first control FET is connected to a first supply voltage through said first control FET paddle;
said second control FET is connected to a second supply voltage through said second control FET paddle.

17. The dual power converter package of claim 12 , wherein said source of said first sync FET and said source of said second sync FET are configured to be connected to ground through said sync FET paddle.

18. The dual power converter package of claim 12 , wherein said first control FET and said first sync FET form a first half-bridge circuit and said second control FET and said second sync FET form a second half-bridge circuit.

19. The dual power converter package of claim 12 , wherein said driver IC external to said leadframe is configured to sense a current through said first control FET and/or a current through said second control FET.

20. A dual power converter package comprising:
a leadframe comprising:
a first control FET paddle configured for electrical connection to a drain of a first control FET;
a second control FET paddle configured for electrical connection to a drain of a second control FET;
a sync FET paddle that is continuous, and configured for electrical connection to a source of a first sync FET and a source of a second sync FET, between said source of said first sync FET and said source of said second sync FET;
a plurality of contacts configured to receive control signals for said first and second control FETs and said first and second sync FETs from a driver integrated circuit;
a switched node configured for electrical connection to a source of said first control FET and a drain of said first sync FET; and

an inductor and a capacitor configured for electrical connection between said switched node and ground.

21. The dual power converter package of claim 20 , wherein each one of the plurality of contacts is arranged along a first edge of the leadframe and the switched node is arranged along a second edge of the leadframe that is opposite from the first edge of the leadframe, and wherein the sync FET paddle extends from a third edge of the leadframe to a fourth edge of the leadframe that is opposite from the third edge of the leadframe and between the first edge of the leadframe and the second edge of the leadframe.

22. The dual power converter package of claim 21 , wherein the first control FET paddle is arranged along the third edge of the leadframe and the second control FET paddle is arranged along the fourth edge of the leadframe, and wherein the first control FET paddle extends towards the fourth edge of the leadframe and the second control FET paddle and the second control FET paddle extends towards the third edge of the leadframe and the first control FET paddle.

Assignees

• Infineon Technologies Americas Corp

Inventors

• Cho Eung San
• Clavette Dan

Classifications

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/871

  Bond wires and strap connectors · CPC title

• H10W72/5475

  multiple bond wires connected to common bond pads at both ends of the wires · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title