Fabrication of vertical field effect transistors with uniform structural profiles

Patent metadata

Field	Value
Publication number	US-9799570-B1
Application number	US-201715430766-A
Country	US
Kind code	B1
Filing date	Feb 13, 2017
Priority date	Feb 13, 2017
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

Semiconductor devices are fabricated with vertical field effect transistor (FET) devices having uniform structural profiles. Semiconductor fabrication methods for vertical FET devices implement a process flow to fabricate dummy fins within isolation regions to enable the formation of vertical FET devices with uniform structural profiles within device regions. Sacrificial semiconductor fins are formed in the isolation regions concurrently with semiconductor fins in the device regions, to minimize/eliminate micro-loading effects from an etch process used for fin patterning and, thereby, form uniform profile semiconductor fins. The sacrificial semiconductor fins within the isolation regions also serve to minimize/eliminate non-uniform topography and micro-loading effects when planarizing and recessing conductive gate layers and, thereby. form conductive gate structures for vertical FET devices with uniform gate lengths in the device regions. The sacrificial semiconductor fins are subsequently removed and replaced with insulating material to form the dummy fins.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device, comprising:
forming a substrate comprising a lower source/drain layer disposed between a base semiconductor substrate and a first layer of semiconductor material;
forming a shallow trench isolation (STI) layer through a portion of the first layer of semiconductor material, the lower source/drain layer and into an upper portion of the semiconductor substrate to form an isolation region, wherein the isolation region defines a first device region comprising a first lower source/drain region and a second device region comprising a second lower source/drain region;
recessing the STI layer;
forming a second layer of semiconductor material on the recessed STI layer in the isolation region;
concurrently patterning the first and second layers of semiconductor material using a first etch process to form an array of vertical semiconductor tins in the first and second device regions and the isolation region;
forming a lower insulating spacer on the first and second lower source/drain regions and the STI layer;
forming a conductive gate structure on the lower insulating spacer and surrounding sidewalls of the vertical semiconductor fins in the first and second device regions and the isolation region;
forming an upper insulating spacer on the conductive gate structure;
etching away the vertical semiconductor fins in the isolation region using a second etch process which is selective to the vertical semiconductor fins in the first and second device regions, to form trenches down to the STI layer in the isolation, region; and
filling the trenches in the isolation region with insulating material to form vertical dummy fins in the isolation region.

2. The method of claim 1 , further comprising epitaxially growing upper source/drain regions on exposed upper portions of the vertical semiconductor tins in the first and second device regions.

3. The method of claim 1 , wherein the first layer of semiconductor material comprises a layer of monocrystalline semiconductor material, and wherein the second layer of semiconductor material comprises a layer of amorphous or polycrystalline semiconductor material.

4. The method of claim 1 , wherein the first layer of semiconductor material comprises monocrystalline silicon and wherein the second layer of semiconductor material comprises amorphous silicon germanium or polycrystalline silicon germanium.

5. The method of claim 1 , wherein the first etch process comprises a dry etch process having an etch chemistry that is non-selective to the first and second layers of semiconductor material, and wherein the second etch process comprises a dry or wet etch process having an etch chemistry that is selective to the first layer of semiconductor material.

6. The method of claim 1 , wherein the vertical semiconductor fins in the first and second device regions and the vertical dummy tins in the isolation region have substantially a same width and are spaced by substantially a same pitch.

7. The method of claim 1 , wherein filling the trenches in the isolation region with insulating material to form the vertical dummy fins in the isolation region comprises filling the trenches with a nitride material.

8. The method of claim 1 , wherein forming the conductive gate structure on the lower insulating spacer and surrounding the sidewalls of the vertical semiconductor fins in the first and second device regions and the isolation region, comprises:
forming a conformal layer of gate dielectric material to cover the vertical semiconductor fins and the lower insulating spacer in the first and second device regions and the isolation region;
depositing a layer of conductive material to fill spaces between the vertical semiconductor fins in the first and second device regions and the isolation region with conductive material; and
recessing the layer of conductive material down to a target level below an upper surface of the vertical semiconductor fins in the first and second device regions and the isolation region, wherein the target level defines a gate length of the conductive gate structure of the vertical semiconductor fins in the first and second device regions.

9. The method of claim 1 , wherein forming the substrate comprises
epitaxially growing the lower source/drain layer on a surface of the base semiconductor substrate; and
epitaxially growing the first layer of semiconductor material on the lower source/drain layer.

Assignees

• IBM

Inventors

• Cheng Kangguo

Classifications

• H10P50/242

  of Group IV materials · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/011

  of isolation regions comprising dielectric materials · CPC title

• H10W10/10

  Isolation regions comprising dielectric materials · CPC title