Land side and die side cavities to reduce package z-height

US9799556B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9799556-B2
Application numberUS-201615057013-A
CountryUS
Kind codeB2
Filing dateFeb 29, 2016
Priority dateSep 28, 2012
Publication dateOct 24, 2017
Grant dateOct 24, 2017

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.

First claim

Opening claim text (preview).

What is claimed is: 1. A method comprising: drilling a first cavity in a first side of a package substrate and drilling a second cavity in the first side of the package substrate, adjacent to the first cavity; forming a contact material within the first cavity and the second cavity; mounting a first component within the first cavity, and forming a solder ball within the second cavity, wherein the first component protrudes from the package substrate by a distance less than or equal to a thickness of the solder ball; and reflowing the solder ball to couple the package substrate to a circuit board. 2. The method of claim 1 wherein the first component is a capacitor. 3. The method of claim 1 wherein the drilling is performed using a laser drill. 4. The method of claim 1 wherein the package substrate comprises a plurality of buildup layers and wherein the first cavity extends through one or more buildup layers. 5. A method of forming a semiconductor device comprising: providing a package substrate having a die side and a land side opposite the die side; forming a plurality of land side cavities within the land side of the package substrate; forming at least one land side component cavity within the land side of the package substrate; attaching a component within the land side component cavity; attaching a die to the die side of the package substrate; and attaching the land side of the package substrate to a first side of a printed circuit board (PCB) by a plurality of solder balls, wherein each of the plurality solder balls is located in a corresponding one of the plurality of land side cavities within the land side of the package substrate, wherein the component protrudes from the package substrate by a distance less than or equal to a thickness of the plurality of solder balls. 6. The method of claim 5 wherein forming the plurality of land side cavities comprises drilling. 7. The method of claim 6 wherein the drilling comprises laser drilling. 8. The method of claim 5 , wherein attaching the component within the land side component cavity includes attaching a capacitor within the land side component cavity. 9. The method of claim 5 further comprising forming a plurality of PCB cavities with the first side of the PCB, wherein each of the plurality of solder balls is located in a corresponding one of the PCB cavities. 10. A method of forming a semiconductor device comprising: providing a package substrate having a die side and a land side opposite the die side; attaching a die to the die side of the package substrate; forming at least one land side component cavity within the land side of the package substrate; attaching a component within the land side component cavity; forming a plurality of PCB cavities in a first side of a printed circuit board (PCB); and attaching the land side of the package substrate to the first side of the printed circuit board (PCB) by a plurality of solder balls, wherein each of a plurality of solder balls is located in a corresponding one of the plurality of PCB cavities within the first side of the printed circuit board (PCB), and wherein the component protrudes from the package substrate by a distance less than or equal to a thickness of the plurality of solder balls. 11. The method of claim 10 wherein forming the plurality of PCB cavities comprises drilling. 12. The method of claim 11 wherein the drilling comprises laser drilling. 13. The method of claim 10 , wherein attaching the component within the land side component cavity includes attaching a capacitor within the land side component cavity.

Assignees

Inventors

Classifications

  • comprising holes having chips therein · CPC title

  • Fan-out layouts · CPC title

  • between stacked chips · CPC title

  • Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

  • on active surfaces of flip-chip devices, e.g. underfills · CPC title

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Frequently asked questions

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What does patent US9799556B2 cover?
A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surfac…
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification H10W70/68. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 24 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).