Method of manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-9799551-B2
Application number	US-201615016286-A
Country	US
Kind code	B2
Filing date	Feb 5, 2016
Priority date	May 27, 2015
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

A method of manufacturing a semiconductor device may include forming an insulating layers on a substrate, forming a plurality of holes in an upper portion of the insulating layer, forming a mask layer having openings exposing at least a first set of the plurality of holes, etching a lower portion of the insulating layer exposed by one of the plurality of holes which is exposed by the mask layer to form a through hole in the insulating layer in combination with the one of the plurality of holes, and forming a conductive structure in the through hole.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming first and second insulating layers on a substrate;
forming a first mask pattern on the second insulating layer;
forming an interconnection contact hole in the second insulating layer using the first mask pattern as an etch mask, the interconnection contact hole exposing the first insulating layer;
forming a second mask pattern having an opening exposing the interconnection contact hole, the second mask pattern different from the first mask pattern;
etching the first insulating layer exposed by the opening of the second mask pattern to form a contact hole in the first insulating layer, wherein the contact hole is formed to have sidewalls aligned with sidewalls of the interconnection contact hole;
removing the first mask pattern and the second mask pattern after the etching the first insulating layer exposed by the opening of the second mask pattern; and
forming an interconnection structure in the contact hole and the interconnection contact hole.

2. The method of claim 1 , wherein the first mask pattern is a hard mask pattern,
wherein the forming the hard mask pattern comprises:
forming a hard mask layer on the second insulating layer;
forming spacers on the hard mask layer; and
etching the hard mask layer exposed by the spacers.

3. The method of claim 2 , wherein the forming the spacers comprises:
forming a sacrificial pattern on the hard mask layer;
forming a spacer layer conformally covering a top surface of the hard mask layer and a surface of the sacrificial pattern on the hard mask layer;
removing the spacer layer formed on the top surface of the hard mask layer and a top surface of the sacrificial pattern; and
selectively removing the sacrificial pattern.

4. The method of claim 2 , wherein the hard mask pattern is used as an etching mask to form the interconnection contact hole and the contact hole.

5. The method of claim 2 , wherein the hard mask pattern is removed after the second mask pattern is removed to expose a top surface of the second insulating layer.

6. The method of claim 1 , wherein the contact hole is formed to vertically overlap the interconnection contact hole.

7. The method of claim 1 , wherein the forming the interconnection structure comprises:
forming a conductive layer filling the contact hole and the interconnection contact hole on the second insulating layer; and
performing a polishing process on the conductive layer until a top surface of the second insulating layer is exposed.

8. The method of claim 1 ,
wherein an interlayer insulating layer including a lower contact is provided to the substrate on which the first and second insulating layers are formed,
wherein the interconnection contact hole is positioned over the lower contact to vertically overlap the lower contact,
wherein the opening in the second mask pattern vertically overlaps the lower contact,
wherein the contact hole formed by etching the first insulating layer exposes the lower contact, and
wherein the interconnection structure contacts the lower contact.

9. The method of claim 8 ,
wherein the forming the interconnection contact hole in the second insulating layer comprises forming a plurality of holes in the second insulating layer,
wherein the second mask pattern has openings exposing at least a set of the plurality holes,
wherein the contact hole of the first insulating layer forms a through hole in combination with a hole formed in the second insulating layer,
wherein the interconnection structure is formed in the through hole and is formed of a conductive structure.

10. The method of claim 1 , wherein the second mask pattern is formed on the first mask pattern.

11. The method of claim 10 , wherein the first mask pattern includes a plurality of openings in a cross-sectional view, and the second mask pattern exposes a first set of the plurality of openings of the first mask pattern and covers a second set of the plurality of openings of the first mask pattern.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Ahn Jongseon

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/085 Primary

  involving intermediate temporary filling with material · CPC title

• H01L21/0337

  Electricity · mapped topic