Apparatus and method for propagating conditionally evaluated values in SIMD/vector execution using an input mask register

Patent metadata

Field	Value
Publication number	US-9798541-B2
Application number	US-201113997183-A
Country	US
Kind code	B2
Filing date	Dec 23, 2011
Priority date	Dec 23, 2011
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

An apparatus and method for propagating conditionally evaluated values are disclosed. For example, a method according to one embodiment comprises: reading each value contained in an input mask register, each value being a true value or a false value and having a bit position associated therewith; for each true value read from the input mask register, generating a first result containing the bit position of the true value; for each false value read from the input mask register following the first true value, adding the vector length of the input mask register to a bit position of the last true value read from the input mask register to generate a second result; and storing each of the first results and second results in bit positions of an output register corresponding to the bit positions read from the input mask register.

First claim

We claim:

1. A method for propagating conditionally evaluated values comprising operations of:
reading each value contained in an input mask register, each value being a true value or a false value and having a bit position associated therewith;
for each true value read from the input mask register, generating a first result containing the bit position of the true value;
for each false value read from the input mask register following a first true value in bit position, adding a vector length of the input mask register to a bit position of a last true value in bit position read from the input mask register to generate a second result; and
storing each of the first results and second results in bit positions, of an output register, corresponding to bit positions read from the input mask register.

2. The method as in claim 1 further comprising:
for each false value read from the input mask register prior to the first true value in bit position, generating a third result containing the bit position of the false value read from the input mask register prior to the first true value; and
storing each of the third results in bit positions, of the output register, corresponding to positions read from the input mask register.

3. The method as in claim 1 further comprising:
reading an immediate value and performing the operations only if the immediate value is set to a first value.

4. The method as in claim 3 wherein if the immediate value is not set to the first value then performing a second set of operations.

5. The method as in claim 4 wherein the second set of operations comprises:
reading each value contained in the input mask register, each value being a true value or a false value and having a bit position associated therewith;
for each true value read from the input mask register, generating a third result containing the bit position of the true value added to the vector length; and
storing each of the third results in bit positions, of the output register, corresponding to bit positions read from the input mask register.

6. The method as in claim 5 further comprising:
storing results of the third results to bit positions, of the output register, corresponding to bit positions read from the input mask register following the first true value in bit position that contain a false value.

7. The method as in claim 6 further comprising:
for each false value read from the input mask register prior to the first true value in bit position, storing the bit position of the false value read from the input mask register prior to the first true value in the output register in a corresponding bit position of the output register.

8. A processor to execute one or more instructions to perform operations of:
reading each value contained in an input mask register, each value being a true value or a false value and having a bit position associated therewith;
for each true value read from the input mask register, generating a first result containing the bit position of the true value;
for each false value read from the input mask register following a first true value in bit position, adding a vector length of the input mask register to a bit position of a last true value in bit position read from the input mask register to generate a second result; and
storing each of the first results and second results in bit positions, of an output register, corresponding to bit positions read from the input mask register.

9. The processor as in claim 8 to execute the one or more instructions to perform further operations of:
for each false value read from the input mask register prior to the first true value in bit position, generating a third result containing the bit position of the false value read from the input mask register prior to the first true value; and
storing each of the third results in bit positions, of the output register, corresponding to bit positions read from the input mask register.

10. The processor as in claim 8 to execute the one or more instructions to perform further operations of:
reading an immediate value and performing the operations only if the immediate value is set to a first value.

11. The processor as in claim 10 wherein if the immediate value is not set to the first value then the processor is to perform a second set of operations.

12. The processor as in claim 11 wherein the second set of operations comprises:
reading each value contained in the input mask register, each value being a true value or a false value and having a bit position associated therewith;
for each true value read from the input mask register, generating a third result containing the bit position of the true value added to the vector length; and
storing each of the third results in bit positions, of the output register, corresponding to bit positions read from the input mask register.

13. The processor as in claim 12 to execute the one or more instructions to perform further operations of:
storing results of the third results to bit positions, of the output register, corresponding to bit positions read from the input mask register following the first true value in bit position that contain a false value.

14. The processor as in claim 13 to execute the one or more instructions to perform further operations of:
for each false value read from the input mask register prior to the first true value in bit position, storing the bit position of the false value read from the input mask register prior to the first true value in the output register in a corresponding bit position of the output register.

15. A system comprising:
a memory for storing instructions and data;
a processor to execute one of the instructions to perform operations of:
reading each value contained in an input mask register, each value being a true value or a false value and having a bit position associated therewith;
for each true value read from the input mask register, generating a first result containing the bit position of the true value;
for each false value read from the input mask register following a first true value in bit position, adding a vector length of the input mask register to a bit position of a last true value in bit position read from the input mask register to generate a second result; and
storing each of the first results and second results in bit positions, of an output register, corresponding to bit positions read from the input mask register.

16. The system as in claim 15 wherein the processor is to execute the one instruction to perform further operations of:
for each false value read from the input mask register prior to the first true value in bit position, generating a third result containing the bit position of the false value read from the input mask register prior to the first true value; and
storing each of the third results in bit positions, of the output register, corresponding to bit positions read from the input mask register.

17. The system as in claim 15 wherein the processor is to execute the one instruction to perform further operations of:
reading an immediate value and performing the operations only if the immediate value is set to a first value.

18. The system as in claim 17 wherein if the immediate value is not set to the first value then the processor is to perform a second set of operations.

19. The system as in claim 18 wherein the second set of operations comprises:
reading each value contained in the input mask register, each value being a true value or a false value and having a bit pos

Assignees

• Bharadwaj Jayashankar
• Vasudevan Nalini
• Lee Victor W
• Kim Daehyun
• Hartono Albert
• Baghsorkhi Sara S
• Intel Corp

Inventors

• Bharadwaj Jayashankar
• Vasudevan Nalini
• Lee Victor W
• Kim Daehyun
• Hartono Albert
• Baghsorkhi Sara S

Classifications

• G06F9/30032

  Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE · CPC title

• G06F9/30098

  Register arrangements · CPC title

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/3877

  using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12) · CPC title

• G06F9/30018 Primary

  Bit or string instructions · CPC title