In-cell touch panel and display device
US-9519374-B2 · Dec 13, 2016 · US
US9798205B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9798205-B2 |
| Application number | US-201514433664-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 28, 2015 |
| Priority date | Dec 18, 2014 |
| Publication date | Oct 24, 2017 |
| Grant date | Oct 24, 2017 |
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Official abstract text for this publication.
A panel having touch function is disclosed. The panel includes a plurality of films, a plurality of touch electrodes arranged on different film layers, a plurality of leading wires respectively corresponding to the touch electrodes, and a touch chip. The leading wires electrically connect the touch electrodes to the touch chip, wherein the leading wires connecting a portion of the touch electrodes are arranged on a first film layer of the film layers and the leading wires connecting other portions of the touch electrodes are arranged on a second film layer of the film layers. In addition, a display device is also disclosed. In this way, the short circuit is avoided, and the possibility of failed touch electrode is also reduced.
Opening claim text (preview).
What is claimed is: 1. A panel having touch functions, comprising: a plurality of films, a plurality of touch electrodes arranged on different film layers, a plurality of leading wires respectively corresponding to the touch electrodes, and a touch chip, the leading wires electrically connect the touch electrodes to the touch chip, wherein the leading wires connecting a portion of the touch electrodes are arranged on a first film layer of the film layers, and the leading wires connecting other portions of the touch electrodes are arranged on a second film layer of the film layers; wherein the pixel electrodes are arranged on a third film layer of the film layers; wherein the panel further comprises an array substrate, and the touch electrodes are made by a common electrode layer of the array substrate; wherein the panel further comprises at least one pixel electrode and at least one thin film transistor (TFT), the pixel electrode is arranged on the third film layer, the TFT is arranged on a fourth film layer of the film layers, and the TFT electrically connects to the pixel electrode via a through hole; wherein the film layers are arranged on the array substrate; wherein the fourth film layer is arranged on the array substrate, the second film layer is arranged on the fourth film layer, the first film layer is arranged on the second film layer, the third film layer is arranged on the first film layer, and the pixel electrode is arranged on a surface of the third film layer away from the first film layer. 2. The panel as claimed in claim 1 , wherein the leading wires are arranged in parallel one by one, and two adjacent leading wires are arranged on different film layers. 3. The panel as claimed in claim 1 , wherein the leading wires electrically connect with corresponding touch electrodes via through holes. 4. The panel as claimed in claim 1 , wherein the touch electrodes are arranged in a matrix.
Insulating layers (G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence) · CPC title
by capacitive means · CPC title
Wiring, e.g. gate line, drain line · CPC title
pixel · CPC title
Digitisers structurally integrated in a display · CPC title
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