Manufacturing method of a graphene-based electrochemical sensor, and electrochemical sensor

Patent metadata

Field	Value
Publication number	US-9797860-B2
Application number	US-201514986123-A
Country	US
Kind code	B2
Filing date	Dec 31, 2015
Priority date	Jun 14, 2012
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

A manufacturing method of an electrochemical sensor comprises forming a graphene layer on a donor substrate, laminating a film of dry photoresist on the graphene layer, removing the donor substrate to obtain an intermediate structure comprising the film of dry photoresist and the graphene layer, and laminating the intermediate structure onto a final substrate with the graphene layer in electrical contact with first and second electrodes positioned on the final substrate. The film of dry photoresist is then patterned to form a microfluidic structure on the graphene layer and an additional dry photoresist layer is laminated over the structure. In one type of sensor manufactured by this process, the graphene layer acts as a channel region of a field-effect transistor, whose conductive properties vary according to characteristics of an analyte introduced into the microfluidic structure.

First claim

The invention claimed is:

1. A device, comprising:
a semiconductor substrate;
a microfluidic chamber formed on the substrate;
a graphene layer forming a wall of the microfluidic chamber and configured to act as a channel region of a field-effect transistor;
a first electrode configured to act as a source of the field-effect transistor; and
a second electrode configured to act as a drain of the field-effect transistor,
wherein the first and second electrodes are positioned on the substrate on opposite sides of the microfluidic chamber, and
wherein the graphene layer is formed over the first and second electrodes and extends outside a region between the first and second electrodes.

2. The device of claim 1 , comprising a third electrode at least partially disposed within the microfluidic chamber and configured to act as a gate of the field-effect transistor, the third electrode being spaced apart from the graphene layer, the third electrode at least partially disposed in an air gap configured to receive a fluid.

3. The device of claim 2 , comprising:
a structural layer positioned over the graphene layer, the structural layer forming at least one additional wall of the microfluidic chamber; and
a cover layer positioned over the structural layer,
wherein the third electrode at least partially extends through the cover layer.

4. The device of claim 3 wherein each of the structural layer and the cover layer includes at least one layer of dry resist.

5. The device of claim 1 wherein the graphene layer is positioned on the substrate and a layer of dry resist is positioned over the graphene layer, the microfluidic chamber comprising a buried cavity formed in the layer of dry resist directly over the graphene layer.

6. The device of claim 5 , comprising:
an inlet aperture formed in the layer of dry resist; and
a buried inlet channel extending between and placing in fluid contact the inlet aperture and the microfluidic chamber.

7. The device of claim 6 , comprising:
an outlet aperture formed in the layer of dry resist; and
a buried outlet channel extending between and placing in fluid contact the outlet aperture and the microfluidic chamber.

8. A device, comprising:
a substrate;
a first electrode on the substrate, the first electrode configured to act as a source of a field-effect transistor;
a second electrode on the substrate, the second electrode configured to act as a drain of the field-effect transistor;
a graphene layer on the substrate and the first and second electrodes, the graphene layer configured to act as a channel region of the field-effect transistor, the graphene layer being formed over the first and second electrodes and extending outside a region between the first and second electrodes; and
a structural layer on the graphene layer;
a microfluidic chamber, wherein the structural layer and the graphene layer form at least one wall of the microfluidic chamber, and
wherein the first and second electrodes are on opposite sides of the microfluidic chamber.

9. The device of claim 8 , comprising a third electrode at least partially disposed within the microfluidic chamber and configured to act as a gate of the field-effect transistor, the third electrode being spaced apart from the graphene layer, the third electrode at least partially disposed in an air gap configured to receive a fluid.

10. The device of claim 9 , comprising:
a cover layer positioned over the structural layer,
wherein the third electrode at least partially extends through the cover layer.

11. The device of claim 10 wherein each of the structural layer and the cover layer includes at least one layer of dry resist.

12. The device of claim 10 , comprising:
an inlet aperture formed in the cover layer; and
a buried inlet channel extending between and placing in fluid contact the inlet aperture and the microfluidic chamber.

13. The device of claim 12 , comprising:
an outlet aperture formed in the cover layer; and
a buried outlet channel extending between and placing in fluid contact the outlet aperture and the microfluidic chamber.

14. A method, comprising:
laminating a first layer of dry resist onto a graphene layer;
laminating the graphene layer and the first layer of dry resist onto a substrate that includes a first electrode configured to act as a source of the field-effect transistor and a second electrode configured to act as a drain of the field-effect transistor, wherein the graphene layer is configured to act as a channel of the field-effect transistor; and
removing at least one portion of the first layer of dry resist to form a microfluidic chamber, wherein each of the first layer of dry resist and the graphene layer forms at least one wall of the microfluidic chamber.

15. The method of claim 14 , comprising:
providing a third electrode configured to act as a gate of the field-effect transistor.

16. The method of claim 15 , comprising:
laminating a second layer of dry resist onto the first layer of dry resist;
forming a first aperture in the second layer of dry resist; and
at least partially inserting the third electrode into the first aperture.

17. The method of claim 16 , comprising:
forming a second aperture in the second layer of dry resist, the second aperture being in fluid communication with the microfluidic chamber.

18. The method of claim 17 , comprising:
forming a third aperture in the second layer of dry resist, the third aperture being in fluid communication with the microfluidic chamber.

19. The device of claim 1 , wherein the first electrode and the second electrode extend over a first side of the substrate, and the graphene layer extends over the first side of the substrate and is in electrical contact with the first and second electrodes, and wherein the device comprises:
a structural layer of dry resist extending on the graphene layer; and
a fluidic path extending through a thickness of the structural layer and on the graphene layer, wherein the fluidic path is disposed entirely between the first and second electrodes.

20. The device of claim 8 , comprising:
a fluidic path extending through a thickness of the structural layer and on the graphene layer, wherein the fluidic path is disposed entirely between the first and second electrodes.

21. The method of claim 14 , comprising:
forming a first electrode over a first side of the substrate, the first electrode being in electrical contact with the graphene layer;
forming a second electrode over the first side of the substrate, the second electrode being in electrical contact with the graphene layer; and
forming a fluidic path extending through a thickness of the first layer of dry resist and on the graphene layer, wherein the fluidic path is disposed entirely between the first and second electrodes.

Assignees

• St Microelectronics Srl

Inventors

• Accardi Corrado
• Loverso Stella
• Ravesi Sebastiano
• Sparta Noemi Graziana

Classifications

• G01N27/414 Primary

  Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS · CPC title

• H01L29/66

  Electricity · mapped topic

• H01L29/1606

  Electricity · mapped topic

• H01L29/66053

  Electricity · mapped topic

• B01L3/502707

  characterised by the manufacture of the container or its components · CPC title