Successive approximation analog-to-digital converter (ADC) with dynamic search algorithm

Patent metadata

Field	Value
Publication number	US-9793915-B2
Application number	US-201615238056-A
Country	US
Kind code	B2
Filing date	Aug 16, 2016
Priority date	Apr 9, 2013
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logic modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage.

First claim

What is claimed is:

1. A method of an analog-to-digital converter, comprising:
obtaining, with the analog-to-digital converter, a digital output code representative of an analog input voltage by updating the digital output code one or more times; and
outputting a flag signal that indicates a timing relationship between a number of updates used to obtain the digital output code representative of the analog input voltage and a baseline number of updates.

2. The method of claim 1 , wherein said outputting comprises generating the flag signal such that the flag signal indicates less than the baseline number of updates were used to obtain the digital output code.

3. The method of claim 1 , wherein said outputting comprises generating the flag signal such that the flag signal indicates more than the baseline number of updates were used to obtain the digital output code.

4. The method of claim 1 , wherein said outputting comprises generating the flag signal such that flag signal indicates the baseline number of updates were used to obtain the digital output code.

5. The method of claim 1 , wherein said outputting comprises generating the flag signal such that the flag signal indicates how many more updates than the baseline number of updates were used to obtain the digital output code.

6. The method of claim 1 , wherein said outputting comprises generating the flag signal such that the flag signal indicates how many fewer updates than the baseline number of updates were used to obtain the digital output code.

7. A successive approximation analog-to-digital converter, comprising:
a digital-to-analog converter operable to generate a reference voltage based on a digital reference code;
a comparator operable to compare an analog input voltage to the reference voltage generated by the digital-to-analog converter and generate a comparison output indicative of the comparison; and
a search and decode logic module comprising one or more circuits operable to:
obtain a digital output code representative of the analog input voltage by updating the digital reference code one or more times based on the comparison output; and
generate a flag signal that indicates a timing relationship between a number of updates used to obtain the digital output code representative of the analog input signal and a baseline number of updates.

8. The successive approximation analog-to-digital converter of claim 7 , wherein the one or more circuits of the search and decode logic module are further operable to generate the flag signal such that the flag signal indicates less than the baseline number of updates were used to obtain the digital output code.

9. The successive approximation analog-to-digital converter of claim 7 , wherein the one or more circuits of the search and decode logic module are further operable to generate the flag signal such that the flag signal indicates more than the baseline number of updates were used to obtain the digital output code.

10. The successive approximation analog-to-digital converter of claim 7 , wherein the one or more circuits of the search and decode logic module are further operable to generate the flag signal such that the flag signal indicates the baseline number of updates were used to obtain the digital output code.

11. The successive approximation analog-to-digital converter of claim 7 , wherein the one or more circuits of the search and decode logic module are further operable to generate the flag signal such that the flag signal indicates how many more updates than the baseline number of updates were used to obtain the digital output code.

12. The successive approximation analog-to-digital converter of claim 7 , wherein the one or more circuits of the search and decode logic module are further operable to generate the flag signal such that the flag signal indicates how many fewer updates than the baseline number of updates were used to obtain the digital output code.

13. An apparatus, comprising:
a communication interface operable to receive analog signal; and
a successive approximation analog-to-digital converter operable to:
obtain a digital output code representative of an analog input voltage of the received analog signal by updating the digital output code one or more times based on a relationship between the analog input voltage and a reference voltage specified by the digital output code; and
generate a flag signal that indicates a timing relationship between a number of updates used to obtain the digital output code representative of the analog input voltage and a baseline number of updates.

14. The apparatus of claim 13 , wherein the successive approximation analog-to-digital converter is further operable to generate the flag signal such that the flag signal indicates less than the baseline number of updates were used to obtain the digital output code.

15. The apparatus of claim 13 , wherein the successive approximation analog-to-digital converter is further operable to generate the flag signal such that the flag signal indicates more than the baseline number of updates were used to obtain the digital output code.

16. The apparatus of claim 13 , wherein the successive approximation analog-to-digital converter is further operable to generate the flag signal such that the flag signal indicates the baseline number of updates were used to obtain the digital output code.

17. The apparatus of claim 13 , wherein the successive approximation analog-to-digital converter is further operable to generate the flag signal such that the flag signal indicates how many more updates than the baseline number of updates were used to obtain the digital output code.

18. The apparatus of claim 13 , wherein the successive approximation analog-to-digital converter is further operable to generate the flag signal such that the flag signal indicates how many fewer updates than the baseline number of updates were used to obtain the digital output code.

Assignees

• Maxlinear Inc

Inventors

• Pullela Raja
• Ling Curtis

Classifications

• H03M1/462

  Details of the control circuitry, e.g. of the successive approximation register · CPC title

• H03M1/002

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title

• H03M1/04

  using stochastic techniques · CPC title

• H03M1/44

  Sequential comparisons in series-connected stages with change in value of analogue signal · CPC title

• H03M1/38 Primary

  sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) · CPC title