Light emitting devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9793432-B2
Application number	US-201514955981-A
Country	US
Kind code	B2
Filing date	Dec 1, 2015
Priority date	Aug 26, 2009
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

Light emitting devices and methods of manufacturing the light emitting devices. The light emitting devices include a silicon substrate; a metal buffer layer on the silicon substrate, a patterned distributed Bragg reflector (DBR) on the metal buffer layer; and a nitride-based thin film layer on the patterned DBR and regions between patterns of the DBR.

First claim

What is claimed is:

1. A method of manufacturing a light emitting device, the method comprising:
forming a metal buffer layer on a silicon substrate;
forming an XY material layer on the metal buffer layer, wherein X is at least one of Ti, Cr, Zr, Hf, Nb, and Ta, and Y is at least one of B and B 2 ; and
forming a GaN layer on the XY material layer,
wherein the XY material layer has a first lattice constant and the GaN layer has a second lattice constant greater than the first lattice constant,
wherein the XY material layer applies compressive strain to the GaN layer,
wherein a distributed Bragg reflector (DBR) is between the metal buffer layer and the XY material layer.

2. The method of claim 1 , wherein the metal buffer layer and the XY material layer include a common material.

3. The method of claim 1 , wherein,
the metal buffer layer includes a material of which a difference in lattice constants from the silicon substrate is smaller than a difference in lattice constants from the GaN layer, or a difference in thermal expansion coefficients from the silicon substrate is smaller than a difference in thermal expansion coefficients from the GaN layer.

4. The method of claim 1 , wherein a thickness of the metal buffer layer is in a range of about 1 nm to about 1 μm.

5. The method of claim 1 , wherein, the XY material layer includes a plurality of holes, and
each hole of the plurality of holes has a diameter in a range of 10 nm to 1 μm.

6. The method of claim 5 , wherein the metal buffer layer includes a plurality of holes at a position corresponding to the plurality of holes in the XY material layer.

7. The method of claim 6 , further comprising:
forming an AlN layer on a bottom surface in an inner wall of the plurality of holes.

8. The method of claim 5 , wherein the metal buffer layer is formed to have an amorphous state.

9. A method of manufacturing a light emitting device, the method comprising:
forming a metal buffer layer on a silicon substrate;
forming an XY material layer on the metal buffer layer, wherein X is at least one of Ti, Cr, Zr, Hf, Nb, and Ta, and Y is at least one of B and B2; and
forming a plurality of holes in the XY material layer, each hole of the plurality of holes having a diameter in a range of 10 nm to 1 μm.

10. The method of claim 9 , wherein the metal buffer layer includes a plurality of holes at a position corresponding to the plurality of holes in the XY material layer.

11. The method of claim 10 , further comprising:
forming an MN layer on a bottom surface in an inner wall of the plurality of holes.

12. The method of claim 10 , wherein the metal buffer layer is formed to have an amorphous state.

13. The method of claim 9 , wherein a distributed Bragg reflector (DBR) is between the metal buffer layer and the XY material layer.

14. A method of manufacturing a light emitting device, the method comprising:
forming a metal buffer layer on a silicon substrate;
forming an XY material layer on the metal buffer layer, wherein X is at least one of Ti, Cr, Zr, Hf, Nb, and Ta, and Y is at least one of N, B, and B 2 ; and
forming a plurality of holes in the XY material layer, such that the metal buffer layer includes a plurality of holes at a position corresponding to the plurality of holes in the XY material layer.

15. The method of claim 14 , wherein each hole of the plurality of holes in the XY material layer has a diameter in a range of 10 nm to 1 μm.

16. The method of claim 14 , further comprising:
forming an AlN layer on a bottom surface in an inner wall of the plurality of holes.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jun-Youn
• Min Bok-Ki
• Hong Hyun-Gi
• Lee Jae-Won

Classifications

• Y10S977/893

  Deposition in pores, molding, with subsequent removal of mold · CPC title

• Y10S977/95

  Electromagnetic energy · CPC title

• B82Y20/00

  Nanooptics, e.g. quantum optics or photonic crystals · CPC title

• H01L33/0075

  Electricity · mapped topic

• H01L33/007 Primary

  Electricity · mapped topic