Integrated circuits including LDMOS transistor structures and methods for fabricating LDMOS transistor structures

Patent metadata

Field	Value
Publication number	US-9793394-B1
Application number	US-201615181780-A
Country	US
Kind code	B1
Filing date	Jun 14, 2016
Priority date	Jun 14, 2016
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

Integrated circuits including LDMOS transistor structures and methods for fabricating LDMOS transistor structures are provided. An exemplary method for fabricating an LDMOS transistor structure includes providing a semiconductor-on-insulator (SOI) substrate including a semiconductor layer overlying an insulator layer overlying a bulk layer. The method includes forming a gate structure overlying the substrate. A channel region is formed in the semiconductor layer under the gate structure. The method includes forming a source region overlying the substrate. Further, the method includes forming a drain region overlying the substrate. A drift region is located between the drain region and the gate structure. Also, the method includes forming contacts to the gate structure, the source region, and the drain region.

First claim

What is claimed is:

1. A method for fabricating an LDMOS transistor structure, the method comprising:
providing a substrate including a semiconductor layer overlying an insulator layer overlying a bulk layer;
forming a gate structure overlying the substrate, wherein a channel region is formed in the semiconductor layer under the gate structure;
forming an alignment gate overlying a drift region in the substrate; and
forming a drain region overlying the substrate and self-aligning the drain region with the alignment gate, wherein the drift region is located between the drain region and the gate structure.

2. The method of claim 1 further comprising forming contacts to the gate structure and the drain region.

3. The method of claim 1 further comprising:
forming a source region overlying the substrate; and
forming contacts to the gate structure, the source region, and the drain region.

4. The method of claim 1 further comprising:
forming isolation regions in the substrate, wherein the isolation regions separate a LDMOS device region from a well tap region;
removing the semiconductor layer and the insulator layer to expose the bulk layer in the well tap region; and
forming a contact to the bulk layer in the well tap region.

5. The method of claim 1 further comprising:
forming isolation regions in the substrate, wherein the isolation regions separate a LDMOS device region from a well tap region;
removing the semiconductor layer and the insulator layer in the well tap region to expose the bulk layer;
epitaxially growing a contact region over the bulk layer in the well tap region, wherein forming the drain region comprise epitaxially growing the drain region; and
forming contacts to the contact region, the drain region and the gate.

6. The method of claim 1 further comprising doping a portion of the semiconductor layer to form the drift region.

7. The method of claim 1 further comprising:
removing a portion of the semiconductor layer and a portion of the insulator layer to expose a portion of the bulk layer; and
epitaxially growing the drift region over the portion of the bulk layer, wherein forming the drain region overlying the substrate comprises forming the drain region on the drift region.

8. The method of claim 1 further comprising:
removing a portion of the semiconductor layer and a portion of the insulator layer to expose a portion of the bulk layer; and
epitaxially growing the drift region over the portion of the bulk layer, wherein forming the gate structure overlying the substrate comprises forming the gate structure partially on the semiconductor layer and partially on the drift region, and wherein forming the drain region overlying the substrate comprises forming the drain region on the drift region.

9. A method for fabricating an LDMOS transistor structure, the method comprising:
providing a substrate including a semiconductor layer overlying an insulator layer overlying a bulk layer;
forming isolation regions in the substrate, wherein the isolation regions separate a LDMOS device region from a well tap region;
removing the semiconductor layer and the insulator layer to expose the bulk layer in the well tap region; and
forming a gate structure overlying the semiconductor layer in the LDMOS device region, wherein a channel region is formed in the semiconductor layer under the gate structure.

10. The method of claim 9 further comprising forming contacts to the bulk layer in the well tap region and to the gate structure.

11. The method of claim 9 further comprising:
forming a drain region overlying the substrate, wherein a drift region is located between the drain region and the gate structure.

12. The method of claim 9 further comprising:
forming a source region overlying the substrate; and
forming a drain region overlying the substrate, wherein a drift region is located between the drain region and the gate structure.

13. The method of claim 9 further comprising:
forming a source region overlying the substrate;
forming a drain region overlying the substrate, wherein a drift region is located between the drain region and the gate structure; and
forming contacts to the bulk layer in the well tap region, to the gate structure, to the source region, and to the drain region.

14. The method of claim 9 further comprising:
forming a drain region overlying the substrate, wherein a drift region is located between the drain region and the gate structure; and
forming an alignment gate overlying the drift region, wherein forming the drain region comprises self-aligning the drain region with the alignment gate.

15. A method for fabricating an LDMOS transistor structure, the method comprising:
providing a substrate including a semiconductor layer overlying an insulator layer overlying a bulk layer;
removing a portion of the semiconductor layer and a portion of the insulator layer to expose a portion of the bulk layer; and
epitaxially growing a drift region over the portion of the bulk layer.

16. The method of claim 15 further comprising forming a gate structure overlying the substrate, wherein a channel region is formed in the semiconductor layer under the gate structure.

17. The method of claim 16 further comprising forming a drain region on the drift region, wherein the drift region is located between the drain region and the gate structure.

18. The method of claim 17 further comprising forming a source region overlying the substrate.

19. The method of claim 18 further comprising forming contacts to the gate structure, the source region, and the drain region.

20. The method of claim 16 further comprising forming contacts to the gate structure and the drain region.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Zhu Ming
• Lim Shi Ya Phyllis
• Li Pinghui
• Nga Yiang Aun

Classifications

• H01L29/161

  Electricity · mapped topic

• H01L29/0653

  Electricity · mapped topic

• H01L29/66681

  Electricity · mapped topic

• H01L29/1095

  Electricity · mapped topic

• H01L29/24

  Electricity · mapped topic