Method of manufacturing a semiconductor device

Patent metadata

Field	Value
Publication number	US-9793291-B2
Application number	US-201615142365-A
Country	US
Kind code	B2
Filing date	Apr 29, 2016
Priority date	May 21, 2015
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

A method of manufacturing a semiconductor device, the method including forming a structure on a substrate, the structure including a metal pattern, at least a portion of the metal pattern being exposed; forming a preliminary buffer oxide layer to cover the structure, a metal oxide layer being formed at the exposed portion of the metal pattern; and deoxidizing the metal oxide layer so that the preliminary buffer oxide layer is transformed into a buffer oxide layer.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming a structure on a substrate, the structure including a metal pattern, at least a portion of the metal pattern being exposed;
forming a preliminary buffer oxide layer to cover the structure, a metal oxide layer being formed at the exposed portion of the metal pattern; and
deoxidizing the metal oxide layer to convert the metal oxide layer into a metal of the metal pattern by moving oxygen from the metal oxide layer to the preliminary buffer oxide layer such that the preliminary buffer oxide layer is transformed into a buffer oxide layer.

2. The method as claimed in claim 1 , wherein deoxidizing the metal oxide includes performing a plasma treatment on the structure.

3. The method as claimed in claim 2 , wherein the plasma treatment is performed using an inert gas or a mixture of an inert gas and hydrogen gas.

4. The method as claimed in claim 2 , wherein the plasma treatment is performed at a temperature of about 300° C. to about 600° C.

5. The method as claimed in claim 1 , further comprising, after deoxidizing the metal oxide layer:
anisotropically etching the buffer oxide layer to form a buffer oxide pattern covering at least the metal pattern.

6. The method as claimed in claim 5 , further comprising, after forming the buffer oxide pattern:
wet cleaning a surface of the buffer oxide pattern.

7. The method as claimed in claim 5 , further comprising, after forming the buffer oxide pattern:
performing a plasma treatment on the buffer oxide pattern.

8. The method as claimed in claim 1 , wherein forming the structure includes:
alternately and repeatedly forming insulating interlayers and sacrificial layers on the substrate;
forming a plurality of channel structures through the insulating interlayers and sacrificial layers;
etching the insulating interlayers and sacrificial layers between the channel structures to form an opening exposing an upper surface of the substrate; and
replacing the sacrificial layers exposed by the opening with a metal pattern.

9. The method as claimed in claim 8 , wherein the preliminary buffer oxide layer is conformally formed on a surface of the structure and the exposed upper surface of the substrate.

10. The method as claimed in claim 8 , further comprising, after forming the buffer oxide layer:
forming a common source line to fill the opening.

11. The method as claimed in claim 1 , wherein the structure includes a tunnel insulation pattern, a charge storage pattern, a dielectric pattern, and the metal pattern sequentially stacked, the metal pattern serving as a control gate.

12. The method as claimed in claim 1 , wherein forming the structure includes:
forming metal patterns and a first insulating interlayer on the substrate, the first insulating interlayer filling a gap between the metal patterns; and
forming a second insulating interlayer on the first insulating interlayer, the second insulating interlayer including openings therethrough, an upper portion of each of the metal patterns being exposed by each of the openings.

13. A method of manufacturing a semiconductor device, the method comprising:
alternately and repeatedly forming insulating interlayers and sacrificial layers on a substrate;
forming a plurality of channel structures through the insulating interlayers and sacrificial layers;
etching the insulating interlayers and sacrificial layers between the channel structures to form an opening exposing an upper surface of the substrate;
replacing the sacrificial layers exposed by the opening with gate lines, respectively, to form a structure, each of the gate lines including a metal;
forming a preliminary buffer oxide layer on a sidewall and a top surface of the structure and the upper surface of the substrate exposed by the opening;
performing a plasma treatment on the preliminary buffer oxide layer to form a buffer oxide layer; and
partially etching the buffer oxide layer to form a buffer oxide pattern covering a least each of the gate lines.

14. The method as claimed in claim 13 , wherein the plasma treatment is performed using an inert gas or a mixture of an inert gas and hydrogen gas.

15. The method as claimed in claim 13 , further comprising, after forming the buffer oxide pattern:
wet cleaning a surface of the buffer oxide pattern.

16. The method as claimed in claim 13 , wherein the buffer oxide layer is anisotropically etched.

17. A method of manufacturing a semiconductor device, the method comprising:
forming a plurality of pad patterns and a first insulating interlayer filling a gap between the pad patterns on a substrate;
forming a second insulating interlayer on the first insulating interlayer, the second insulating interlayer including an opening exposing a portion of a surface of the pad pattern;
forming a preliminary buffer oxide layer on a top surface of the second insulating interlayer, a sidewall of the opening, and the surface of the pad pattern exposed by the opening;
performing a plasma treatment on the preliminary buffer oxide layer to transform a portion of the preliminary buffer oxide layer into a buffer oxide layer;
etching the buffer oxide layer to form a buffer oxide pattern exposing the pad pattern; and
wet cleaning the buffer oxide pattern to remove the preliminary buffer oxide,
wherein:
the plasma treatment is performed so that a first portion of the preliminary buffer oxide layer is transformed into a buffer oxide layer and a second portion of the preliminary buffer oxide layer remains,
the first portion of the preliminary buffer oxide layer is higher than a top surface of the pad pattern, and
the second portion of the preliminary buffer oxide layer is lower than a top surface of the pad pattern.

18. The method as claimed in claim 17 , wherein the plasma treatment is performed using an inert gas or a mixture of an inert gas and hydrogen gas.

19. The method as claimed in claim 17 , wherein:
the buffer oxide layer is anisotropically etched, and
the buffer oxide pattern is formed on a sidewall of the opening.

20. The method as claimed in claim 1 , wherein deoxidizing the metal oxide to convert the metal oxide layer into a metal of the metal pattern by moving oxygen from the metal oxide layer to the preliminary buffer oxide layer such that the preliminary buffer oxide layer is transformed into a buffer oxide layer includes:
increasing a density of the preliminary buffer oxide layer, and
lowering a resistance of the metal pattern.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Shin Hyun-Jin
• Kim Hong-Suk
• Kim Jung-Hwan
• Lee Sang-Hoon
• Lim Hun-Hyeong
• Cho Yong-Seok
• Kim Young-Dae
• YANG Han-Vit

Classifications

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10P70/23

  during, before or after processing of insulating materials · CPC title

• H10P50/283

  by chemical means · CPC title

• H10W20/096 Primary

  by contacting with gases, liquids or plasmas · CPC title

• H10W20/076

  in via holes or trenches · CPC title