Circuit configuration and manufacturing processes for vertical transient voltage suppressor (TVS) and EMI filter

Patent metadata

Field	Value
Publication number	US-9748346-B2
Application number	US-201414554010-A
Country	US
Kind code	B2
Filing date	Nov 25, 2014
Priority date	Nov 25, 2014
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

A vertical TVS (VTVS) circuit includes a semiconductor substrate for supporting the VTVS device thereon having a heavily doped layer extending to the bottom of substrate. Deep trenches are provided for isolation between multi-channel VTVS. Trench gates are also provided for increasing the capacitance of VTVS with integrated EMI filter.

First claim

We claim:

1. A multi-channel TVS device integrated with an EMI filter comprising:
a first and a second vertical TVS (VTVS) comprising vertically stacked PN junctions disposed between doped regions of opposite conductivity types disposed in an epitaxial layer supported on a semiconductor substrate wherein each of the first VTVS and second VTVS having a top dopant region disposed underneath a top surface of the substrate connected to a first electrode functioning as an input terminal and a first cathode electrode and a second electrode functioning as an output terminal and a second cathode electrode wherein the first and second VTVS are separated by a deep insulation trench;
the substrate further comprising a heavily doped bottom layer of a first conductivity type functioning as an anode electrode; and
a conductive strip extending laterally over the top of the deep insulation trench wherein the conductive strip is electrically connected to the input terminal and output terminal to function with the stack PN junctions as an integrated EMI filter.

2. The VTVS device of claim 1 further comprising:
additional insulation trenches disposed on outer sides of the first VTVS and the second VTVS filled with a conductive material for functioning with the integrated EMI filter as parallel connected vertical capacitors between the cathode electrodes and the anode electrode.

3. The VTVS device of claim 2 further comprising:
a diffusion region disposed between the additional trenches.

4. The VTVS device of claim 1 wherein:
the deep insulation trench extends vertically below the epitaxial layer and filled with a conductive material composed of polysilicon.

5. The VTVS device of claim 4 wherein:
the polysilicon filled in the deep insulation trench is padded by an oxide layer formed on trench sidewalls and on a trench bottom surface.

6. The VTVS device of claim 2 wherein:
the additional insulation trenches extend vertically below the epitaxial layer and filled with a conductive material composed of polysilicon.

7. The VTVS device of claim 6 wherein:
the polysilicon filled in the additional insulation trenches is padded by an oxide layer formed on trench sidewalls and on a trench bottom surface of the additional insulation trenches.

8. The VTVS device of claim 1 wherein:
the doped regions of opposite conductivity types disposed in the epitaxial layer comprising a dopant well of a second conductivity type encompassing a top dopant region of a first conductivity type.

9. The VTVS device of claim 1 wherein:
the doped regions of opposite conductivity types disposed in the epitaxial layer comprising a P-type well encompassing a top dopant region of an N-type conductivity type.

10. The VTVS device of claim 1 wherein:
the doped regions of opposite conductivity types disposed in the epitaxial layer comprising of a P-type epitaxial layer includes a dopant well of an N-type well encompassing a top dopant region of the P-type conductivity.

11. The VTVS device of claim 2 wherein:
the additional insulation trenches are filled with segments of the conductive material wherein the segments are insulated by an inter-segment insulation layer.

12. The VTVS device of claim 11 wherein:
the segments disposed in the additional insulation trenches are interconnected through trench-tunnels opened in the semiconductor substrate between the additional insulation trenches and the deep insulation trench.

13. The VTVS device of claim 2 wherein:
the additional insulation trenches are formed as encircling loops of trenches filled with the conductive material to function as an inductor.

14. The VTVS device of claim 13 wherein:
the conductive material filled in the encircling loops of trenches are electrically connected to the input terminal and the output terminal through a first metal layer to the first cathode electrode and through a second metal layer to the second cathode electrode of the first VTVS and the second VTVS respectively.

15. The VTVS device of claim 1 wherein:
the heavily doped layer disposed near the bottom surface comprising a dopant region having a dopant concentration of a first conductivity type higher than 1E18/cm3.

16. The VTVS device of claim 1 wherein:
the dopant regions disposed in the epitaxial layer comprising a body region of second conductivity type disposed on an upper portion of the epitaxial layer of a first conductivity type thus forming the vertically stacked PN junction.

Assignees

• Alpha & Omega Semiconductor

Inventors

• Mallikarjunaswamy Shekar
• Bobde Madhur

Classifications

• H10W42/20

  protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons · CPC title

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H01L23/552

  Electricity · mapped topic

• H01L2924/0002

  Electricity · mapped topic

• H01L23/5223

  Electricity · mapped topic