Memory device including delay circuit having gate insulation films with thicknesses different from each other

Patent metadata

Field	Value
Publication number	US-9792976-B2
Application number	US-201615206354-A
Country	US
Kind code	B2
Filing date	Jul 11, 2016
Priority date	Oct 29, 2015
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

Provided is a memory device including a delay circuit having gate insulation films with thicknesses different from each other. The memory device includes a delay circuit configured to input an input signal and output an output signal, and circuit blocks configured to control an operation of reading or writing memory cell data in response to the input signal or the output signal. One of transistors constituting a circuit block has a gate insulation film having such a thickness that an effect of negative biased temperature instability (NBTI) or positive biased temperature instability (PBTI) on the transistors is minimized. The delay circuit may be affected little by a shift in a threshold voltage that may be caused by NTBI or PBTI, and thus, achieve target delay time.

First claim

What is claimed is:

1. A delay circuit comprising:
a first resistor comprising a first set of one or more transistors connected between a source of a power voltage and a first node;
a second resistor comprising a second set of one or more transistors connected between a second node and a ground voltage; and
an inverter comprising a third set of one or more transistors connected between the first node and the second node, the inverter configured to receive an input signal, invert the input signal, and output the inverted input signal as an output signal,
wherein at least one transistor of the first set of one or more transistors has a gate insulation film having a thickness different from that of at least one transistor of the second set of one or more transistors.

2. The delay circuit of claim 1 , wherein the third set of one or more transistors of the inverter comprises:
a first transistor having a source connected to the first node, a drain connected to the output signal, and a gate connected to the input signal; and
a second transistor having a source connected to the second node, a drain connected to the output signal, and a gate connected to the input signal.

3. The delay circuit of claim 2 , wherein a gate insulation film of the first transistor is thicker than gate insulation films of transistors included in the second resistor.

4. The delay circuit of claim 2 , wherein a gate insulation film of the second transistor is thicker than gate insulation films of transistors included in the first resistor.

5. The delay circuit of claim 1 , wherein a gate insulation film of at least one transistor of the first set of one or more transistors is thickest among gate insulation films of transistors included in the inverter, the first resistor, and the second resistor.

6. The delay circuit of claim 1 , wherein the gate insulation film of the at least one transistor of the second set of one or more transistors is thickest among gate insulation films of the transistors included in the inverter, the first resistor, and the second resistor.

7. The delay circuit of claim 1 , wherein the delay circuit further comprises:
a loader comprising at least two capacitors connected to the output signal.

8. The delay circuit of claim 7 , wherein a transistor is implemented as one of the at least two capacitors having a gate insulation film that is thicker than gate insulation films of two or more transistors included in the inverter, the first resistor, and the second resistor.

9. A delay circuit comprising:
a first resistor comprising a first set of one or more transistors connected between a source voltage and a first node;
a second resistor comprising a second set of one or more transistors connected between a second node and a ground voltage;
an inverter comprising a third set of one or more transistors connected between the first node and the second node, the inverter configured to receive an input signal, invert the input signal, and output the inverted input signal as an output signal; and
a loader comprising a plurality of transistors implemented as a plurality of capacitors and connected to the output signal,
wherein gates of the third set of one or more transistors are connected in parallel to the input signal and drains of the third set of one or more transistors are connected to the output signal, and
wherein two or more transistors from among the first set of one or more transistors and the second set of one or more transistors have gate insulation films having thicknesses different from each other.

10. The delay circuit of claim 9 , wherein a gate insulation film of at least one of the plurality of capacitors is thicker than gate insulation films of the first set of one or more transistors.

11. The delay circuit of claim 9 , wherein gate insulation films of the first set of one or more transistors are thicker than gate insulation films of the second set of one or more transistors.

12. The delay circuit of claim 9 , wherein a gate insulation film of at least one of the plurality of capacitors is thicker than gate insulation films of the second set of one or more transistors.

13. The delay circuit of claim 9 , wherein gate insulation films of the second set of one or more transistors are thicker than gate insulation films of the first set of one or more transistors.

14. A delay circuit comprising:
a first resistor comprising at least one first transistor connected between a source of a power voltage and a first node;
a second resistor comprising at least one second transistor connected between a second node and a ground voltage;
an inverter comprising at least one third transistor connected between the first node and the second node, the inverter configured to receive an input signal, invert the input signal, and output the inverted input signal as an output signal; and
a loader comprising a first capacitor connected between the power voltage and the output signal, and a second capacitor connected between the output signal and the ground voltage,
wherein transistors are implemented as the first capacitor and the second capacitor, and
wherein at least one of the first capacitor and the second capacitor has a gate insulation film having a thickness different from that of one or more transistors of the at least one first transistor and the at least one second transistor.

15. The delay circuit of claim 14 , wherein a gate insulation film of the at least one first transistor is thicker than a gate insulation film of the at least one second transistor.

16. The delay circuit of claim 14 , wherein a gate insulation film of the at least one second transistor is thicker than a gate insulation film of the at least one first transistor.

17. The delay circuit of claim 14 ,
wherein a gate insulation film of at least one of the first capacitor and the second capacitor is thickest among gate insulation films of transistors included in the first resistor, the second resistor, and the loader.

18. The delay circuit of claim 14 ,
wherein a gate insulation film of the first capacitor is thicker than a gate insulation film of the at least one second transistor.

19. The delay circuit of claim 14 ,
wherein a gate insulation film of the second capacitor is thicker than a gate insulation film of the at least one first transistor.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yoon Ho-Sung
• Kim Doo-Young

Classifications

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• H01L29/42364

  Electricity · mapped topic

• H03K5/15066

  using bistable devices (H03K5/15093 takes precedence) · CPC title

• G11C11/4076 Primary

  Timing circuits (for regeneration management G11C11/406) · CPC title

• H01L27/108

  Electricity · mapped topic