Semiconductor memory device capable of preventing negative bias temperature instability (NBTI) using self refresh information

Patent metadata

Field	Value
Publication number	US-9281048-B2
Application number	US-201414325852-A
Country	US
Kind code	B2
Filing date	Jul 8, 2014
Priority date	Nov 29, 2013
Publication date	Mar 8, 2016
Grant date	Mar 8, 2016

Abstract

A semiconductor memory device that includes a command decoder, a refresh controller, an oscillator and a delay unit. The command decoder generates a self refresh command, and the oscillator generates an oscillation signal. The refresh controller generates a refresh control signal and a recovery signal in response to the self refresh command and the oscillation signal. The delay unit transitions internal nodes included in the delay unit that are not transitioned during a refresh period in response to the refresh control signal and the recovery signal.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a command decoder configured to generate a self refresh command;
an oscillator configured to generate an oscillation signal;
a refresh controller configured to generate a refresh control signal and a recovery signal in response to the self refresh command and the oscillation signal; and
a delay unit configured to transition voltage levels of internal nodes included in the delay unit during a refresh period, in response to the refresh control signal and the recovery signal.

2. The device according to claim 1 , wherein the refresh control signal is not transitioned during the refresh period.

3. The device according to claim 1 , wherein the refresh control signal and the recovery signal are generated in a self refresh mode.

4. The device according to claim 1 , wherein the delay unit includes a plurality of delay segments each having internal nodes whose voltage levels transition in response to the refresh control signal and the recovery signal.

5. The device according to claim 4 , wherein each of the plurality of delay segments is configured to electrically connect one of its internal nodes to a ground voltage during the refresh period.

6. The device according to claim 4 , wherein each of the plurality of delay segments is configured to electrically connect an internal node located near an input terminal to a ground voltage during the refresh period.

7. The device according to claim 4 , wherein each of the plurality of delay segments comprises:
a plurality of inverters connected to each other in a chain form;
a plurality of p-channel metal-oxide-semiconductor (PMOS) transistors connected to a supply voltage and each of the inverters, and configured to perform a switching operation in response to a first refresh control signal;
a plurality of n-channel metal-oxide-semiconductor (NMOS) transistors connected to a ground voltage and each of the inverters, and configured to perform a switching operation in response to a second refresh control signal; and
a first switch configured to transition voltage levels of some internal nodes located between the inverters in response to the recovery signal.

8. The device according to claim 7 , wherein the first switch includes an NMOS transistor connected between one internal node located between the inverters and the ground voltage, and configured to perform a switching operation in response to the recovery signal.

9. The device according to claim 7 , wherein the first refresh control signal and the second refresh control signal have opposite phases with respect to each other.

10. The device according to claim 7 , wherein the recovery signal has the same phase as the first refresh control signal.

11. A semiconductor memory device, comprising:
a command decoder configured to generate a self refresh command;
an oscillator configured to generate an oscillation signal;
a refresh controller configured to generate a refresh control signal in response to the self refresh command and the oscillation signal; and
a delay unit configured to transition voltage levels of internal nodes included in the delay unit during a refresh period, in response to the refresh control signal.

12. The device according to claim 11 , wherein the delay unit is configured to perform a power gating operation in response to the refresh control signal in the refresh period.

13. The device according to claim 11 , wherein the delay unit includes a plurality of delay segments each having internal nodes whose voltage levels transition in response to the refresh control signal.

14. The device according to claim 13 , wherein each of the plurality of delay segments comprises:
a plurality of inverters connected to each other in a chain form;
a plurality of p-channel metal-oxide-semiconductor (PMOS) transistors connected to a supply voltage and each of the inverters, and configured to perform a switching operation in response to a first refresh control signal;
a plurality of n-channel metal-oxide-semiconductor (NMOS) transistors connected to a ground voltage and each of the inverters, and configured to perform a switching operation in response to a second refresh control signal; and
a first switch configured to transition voltage levels of some of internal nodes located between the inverters in response to the first refresh control signal.

15. The device according to claim 14 , wherein the first switch includes an NMOS transistor connected between one internal node located between the inverters and the ground voltage, and configured to perform a switching operation in response to the first refresh control signal.

16. A semiconductor memory device, comprising:
a refresh controller configured to generate a refresh control signal and a recovery signal in response to a self refresh command and an oscillation signal; and
a delay unit configured to electrically connect at least one of its internal nodes to a ground voltage in response to the recovery signal during a refresh period.

17. The device of claim 16 , wherein the delay unit includes a plurality of inverters including p-channel metal-oxide-semiconductor (PMOS) transistors.

18. The device of claim 16 , wherein the refresh control signal includes a first refresh control signal and a second refresh control signal having different phases from each other.

19. The device of claim 18 , wherein the first refresh control signal is input to p-channel metal-oxide-semiconductor (PMOS) transistors of the delay unit and the second refresh control signal is input to n-channel metal-oxide-semiconductor (NMOS) transistors of the delay unit.

20. The device of claim 16 , wherein the internal node that is connected to the ground voltage is disposed between a pair of inverters of the delay unit.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Byung-Chul
• Kim Yang-Ki
• Jeon Seong-Hwan

Classifications

• G11C11/406

  Management or control of the refreshing or charge-regeneration cycles · CPC title

• G11C2211/4065

  Low level details of refresh operations · CPC title

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C2207/104

  Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs · CPC title

• G11C7/04

  with means for avoiding disturbances due to temperature effects · CPC title