Integrated circuit hierarchical design tool apparatus and method of hierarchically designing an integrated circuit

Patent metadata

Field	Value
Publication number	US-9792399-B2
Application number	US-201314758967-A
Country	US
Kind code	B2
Filing date	Jan 7, 2013
Priority date	Jan 7, 2013
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

An integrated circuit hierarchical design tool apparatus comprises a processor arranged to support a block coupling reconfiguration unit. The block coupling reconfiguration unit is capable of receiving block layout data comprising block placement, terminal location data and intra-block connectivity data. The block coupling reconfiguration unit is arranged to identify from the block layout data a block placement level block having a terminal respectively coupled to a plurality of other block placement level blocks by a plurality of nets, and to provide the block with an additional terminal capable of providing the same function as the terminal. The block coupling reconfiguration unit is also arranged to replace a net of the plurality of nets that is coupled to the terminal with a replacement net coupled to the additional terminal.

First claim

The invention claimed is:

1. An integrated circuit hierarchical design tool apparatus, the apparatus comprising:
a block coupling reconfiguration circuit configured to receive block layout data comprising block placement, terminal location data, and intra-block connectivity data for the integrated circuit, identify from the block layout data a block placement level block having a terminal respectively coupled to a plurality of other block placement level blocks by a plurality of nets, provide the block with an additional terminal capable of providing the same function as the terminal, calculate a location of the additional terminal with respect to the block, identify whether the calculated location of the additional terminal results in net congestion, adjust the location of the additional terminal in response to the identification of the net congestion, and replace a net of the plurality of nets that is coupled to the terminal with a replacement net coupled to the additional terminal, wherein an integrated circuit fabricated with the replacement net has reduced net congestion.

2. The apparatus as claimed in claim 1 , wherein the block coupling reconfiguration circuit is configured to determine whether the net of the plurality of nets is suboptimal, and replace the suboptimal net in response to the net being determined as suboptimal.

3. The apparatus as claimed in claim 2 , wherein determination of the net as being suboptimal comprises determining whether the net exceeds a predetermined length.

4. The apparatus as claimed in claim 3 , wherein the predetermined length corresponds to a maximum signal travel distance at a predetermined clock frequency.

5. The apparatus as claimed in claim 4 , wherein the block layout data relates to a processing system capable of using a plurality of clock signals, the predetermined clock frequency being the fastest of the plurality of clock signals.

6. The apparatus as claimed in claim 1 , wherein the block coupling reconfiguration circuit is configured to provide the net with an in-line sampling unit.

7. The apparatus as claimed in claim 1 , wherein the block coupling reconfiguration circuit is configured to calculate the location of the additional terminal so as to reduce a length of the replacement net.

8. The apparatus as claimed in claim 7 , wherein the block coupling reconfiguration circuit is configured also to calculate the location of the additional terminal so as to reduce a length of a further net and then to define the further net as being coupled to the additional terminal.

9. The apparatus as claimed in claim 1 , wherein the replacement net is shorter than the net.

10. The apparatus as claimed in claim 1 , wherein the block coupling reconfiguration circuit is configured to identify whether the calculated location of the additional terminal results in terminal conflict.

11. The apparatus as claimed in claim 1 , wherein the net is coupled to another terminal of another block of the plurality of other blocks and the replacement net is coupled to the another terminal in place of the net.

12. The apparatus as claimed in claim 1 , wherein the block coupling reconfiguration circuit is configured to analyze the block layout data to find a first block terminal location in respect of a first block identified as coupled to a second block terminal in respect of a second block and a third block terminal in respect of a third block identified as coupled to the second block terminal, identify a suboptimal coupling between the second block terminal and the third block terminal, define an additional second block terminal in respect of the second block, and replace the coupling between the third block terminal and the second block terminal with a replacement coupling between the third block terminal and the additional second block terminal.

13. The apparatus as claimed in claim 1 , wherein the processor is configured to generate data compatible with a block level design unit for hierarchical integrated circuit design.

14. A method of hierarchically fabricating an integrated circuit at a block placement level, the method comprising:
a block coupling reconfiguration unit receiving block layout data comprising block placement, terminal location data and intra-block connectivity data;
the block coupling reconfiguration unit identifying from the block layout data a block placement level block having a terminal respectively coupled to a plurality of other block placement level blocks by a plurality of nets;
the block coupling reconfiguration unit providing the block with an additional terminal capable of providing the same function as the terminal;
the block coupling reconfiguration unit calculating a location of the additional terminal with respect to the block;
the block coupling reconfiguration unit identifying whether the calculated location of the additional terminal results in net congestion;
the block coupling reconfiguration unit adjusting the location of the additional terminal in response to the identification of the net congestion;
the block coupling reconfiguration unit replacing a net of the plurality of nets that is coupled to the terminal with a replacement net coupled to the additional terminal; and
fabricating the integrated circuit, wherein the integrated circuit fabricated with the replacement net has reduced net congestion.

15. An integrated circuit fabricated by a hierarchical design layout tool, comprising:
a set of integrated circuit elements whose position in the integrated circuit is defined by a block coupling reconfiguration unit configured to receive block layout data comprising block placement, terminal location data, and intra-block connectivity data for the integrated circuit, identify from the block layout data a block placement level block having a terminal respectively coupled to a plurality of other block placement level blocks by a plurality of nets, provide the block with an additional terminal capable of providing the same function as the terminal, calculate a location of the additional terminal with respect to the block, identify whether the calculated location of the additional terminal results in net congestion, adjust the location of the additional terminal in response to the identification of the net congestion, and replace a net of the plurality of nets that is coupled to the terminal with a replacement net coupled to the additional terminal, wherein the integrated circuit fabricated with the replacement net has reduced net congestion.

Assignees

• Berkovitz Asher
• Ben-Porat Inbar
• Neeman Yossy
• Nxp Usa Inc

Inventors

• Berkovitz Asher
• Ben-Porat Inbar
• Neeman Yossy

Classifications

• G06F30/394 Primary

  Routing (G06F30/396 takes precedence) · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F17/5081

  Physics · mapped topic

• G06F17/5072 Primary

  Physics · mapped topic