Performing emulated message signaled interrupt handling

Patent metadata

Field	Value
Publication number	US-8996774-B2
Application number	US-201213534511-A
Country	US
Kind code	B2
Filing date	Jun 27, 2012
Priority date	Jun 27, 2012
Publication date	Mar 31, 2015
Grant date	Mar 31, 2015

Abstract

In an embodiment, a processor includes a logic to store a write transaction including an interrupt and data received from a device coupled to the processor to a cache line of a cache memory based on an address in an address queue, and forward an address of the cache line and assert an emulated message signaling interrupt (MSI) signal to an interrupt controller of the processor. Other embodiments are described and claimed.

First claim

What is claimed is:

1. A processor comprising:
a first logic to store a write transaction including an interrupt and data received from a device coupled to the processor to a cache line of a cache memory based on an address in an address queue, and forward an address of the cache line and assert an emulated message signaling interrupt (MSI) signal to an interrupt controller of the processor;
the interrupt controller coupled to the first logic to obtain the data stored in the cac…

Assignees

• Chew Yen Hsiang
• Intel Corp

Inventors

• Chew Yen Hsiang

Classifications

• G06F13/24 Primary

  Physics · mapped topic