Techniques for queueing interrupts in a data processing system

Patent metadata

Field	Value
Publication number	US-9792232-B2
Application number	US-201615334985-A
Country	US
Kind code	B2
Filing date	Oct 26, 2016
Priority date	Nov 16, 2015
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

A method of handling interrupts in a data processing system includes maintaining a first interrupt destination buffer (IDB) for a first interrupt handler routine (IHR) and a second IDB for a second IHR. Whether a received interrupt is associated with the first IHR or the second IHR is determined. In response to the received interrupt being associated with the first IHR, event information associated with the received interrupt is stored in the first IDB. In response to the received interrupt being associated with the second IHR, the event information associated with the received interrupt in stored in the second IDB.

First claim

What is claimed is:

1. A method of handling interrupts in a data processing system, the method comprising:
maintaining, by an interrupt routing controller (IRC), a first interrupt destination buffer (IDB) for a first interrupt handler routine (IHR) and a second IDB for a second IHR;
receiving, by the IRC, an interrupt;
determining, by the IRC, whether the received interrupt is associated with the first IHR or the second IHR;
in response to the received interrupt being associated with the first IHR, storing, by the IRC, event information associated with the received interrupt in the first IDB; and
in response to the received interrupt being associated with the second IHR, storing, by the IRC, the event information associated with the received interrupt in the second IDB, wherein the event information includes an event source number and a generation value that specifies whether a circular buffer associated with a respective one of the first and second IDBs has been completely traversed.

2. The method of claim 1 , wherein the first and second IDBs are maintained in main memory.

3. The method of claim 1 , wherein the first and second IDBs are maintained in a memory associated with the IRC.

4. The method of claim 1 , wherein the first IDB buffers event information for a single event path number and multiple event source numbers.

5. The method of claim 1 , wherein the first IDB is accessed via a first virtual processor thread list that prioritizes interrupts for the first IHR.

6. The method of claim 5 , wherein the first virtual processor thread list provides pointers to headers for the prioritized interrupts in the first IDB.

7. A processing unit for a multithreaded data processing system, the processing unit comprising:
an interrupt source controller (ISC);
an interrupt presentation controller (IPC); and
an interrupt routing controller (IRC) coupled to the ISC and the IPC, wherein the IRC is configured to:
maintain a first interrupt destination buffer (IDB) for a first interrupt handler routine (IHR) and a second IDB for a second IHR;
receive an interrupt;
determine whether the received interrupt is associated with the first IHR or the second IHR;
in response to the received interrupt being associated with the first IHR, store event information associated with the received interrupt in the first IDB; and
in response to the received interrupt being associated with the second IHR, store the event information associated with the received interrupt in the second IDB, wherein the event information includes an event source number and a generation value that specifies whether a circular buffer associated with a respective one of the first and second IDBs has been completely traversed.

8. The processing unit of claim 7 , wherein the first and second IDBs are maintained in main memory.

9. The processing unit of claim 7 , wherein the first and second IDBs are maintained in a memory associated with the IRC.

10. The processing unit of claim 7 , wherein the first IDB buffers event information for a single event path number and multiple event source numbers.

11. The processing unit of claim 7 , wherein the first IDB is accessed via a first virtual processor thread list that prioritizes interrupts for the first IHR.

12. The processing unit of claim 11 , wherein the first virtual processor thread list provides pointers to headers for the prioritized interrupts in the first IDB.

13. A data processing system, comprising:
a memory; and
a processing unit coupled to the memory, wherein the processing unit is configured to:
maintain a first interrupt destination buffer (IDB) for a first interrupt handler routine (IHR) and a second IDB for a second IHR;
receive an interrupt;
determine whether the received interrupt is associated with the first IHR or the second IHR;
in response to the received interrupt being associated with the first IHR, store event information associated with the received interrupt in the first IDB; and
in response to the received interrupt being associated with the second IHR, store the event information associated with the received interrupt in the second IDB, wherein the event information includes an event source number and a generation value that specifies whether a circular buffer associated with a respective one of the first and second IDBs has been completely traversed.

14. The design structure of claim 13 , wherein the first and second IDBs are maintained in main memory.

15. The data processing system of claim 13 , wherein the first and second IDBs are maintained in a memory associated with the IRC.

16. The data processing system of claim 13 , wherein the first IDB buffers event information for a single event path number and multiple event source numbers.

17. The data processing system of claim 13 , wherein the first IDB is accessed via a first virtual processor thread list that prioritizes interrupts for the first IHR and the first virtual processor thread list provides pointers to headers for the prioritized interrupts in the first IDB.

Assignees

• IBM

Inventors

• Arndt Richard L
• Auernhammer Florian A

Classifications

• G06F9/4812 Primary

  by interrupt, e.g. masked · CPC title

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F12/122

  of the least frequently used [LFU] type, e.g. with individual count value · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title