High performance persistent memory

Patent metadata

Field	Value
Publication number	US-9792190-B2
Application number	US-201514752585-A
Country	US
Kind code	B2
Filing date	Jun 26, 2015
Priority date	Jun 26, 2015
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

Embodiments are generally directed to high capacity energy backed memory with off device storage. A memory device includes a circuit board; multiple memory chips that are installed on the circuit board; a controller to provide for backing up contents of the memory chips when a power loss condition is detected; a connection to a backup energy source; and a connection to a backup data storage that is separate from the memory device.

First claim

What is claimed is:

1. A dual in-line memory module (DIMM) for installation in a computer system, the DIMM comprising:
a circuit board having a first side and a second side, the circuit board including a first plurality of electrical contacts on the first side of the circuit board and a second plurality of electrical contacts on the second side for connection with the computing system;
a connector installed in the circuit board of the DIMM, the connector including a connection to receive power from a backup energy source, the backup energy source being separate from the DIMM, the connector being separate from the first plurality and second plurality of electrical contacts;
a plurality of volatile memory chips installed on the circuit board of the DIMM, wherein the plurality of volatile memory chips includes a first set of volatile memory chips installed in the first side of the circuit board and a second set of volatile memory chips installed in the second side of the circuit board; and
a controller installed in the circuit board of the DIMM, the controller to provide for moving contents of the plurality of volatile memory chips in a power loss condition to a non-volatile storage device that is separate from the DIMM.

2. The DIMM of claim 1 , wherein the connection to the backup energy source includes a connection to one or more supercapacitors.

3. The DIMM of claim 1 , wherein backing up contents of the plurality of volatile memory chips includes limiting the contents to be backed up to a partial range of memory based on a setting.

4. A computing system comprising:
a processor for processing of data;
an antenna for transmission or reception of data for the computing system;
a plurality of dual in-line memory modules (DIMMs) installed in the computing system including at least a first set of DIMMs, each DIMM of the first set of DIMMs including:
a circuit board having a first side and a second side, the circuit board including a first set of electrical contacts on the first side and a second set of electrical contacts on the second side for connection with the computing system;
a connector installed in the circuit board of the DIMM, the connector including a connection to receive power from backup energy source, the connector being separate from the first set and second set of electrical contacts;
a plurality of dynamic random access memory (DRAM) chips installed in the circuit board of the DIMM, wherein the plurality of DRAM chips includes a first set of DRAM chips installed in the first side of the circuit board and a second set of DRAM chips installed in the second side of the circuit board, and
a controller installed in the circuit board of the DIMM, the controller to control back up of contents of the plurality of DRAM chips in a power loss condition;

a data storage device to store data for at least the first set of DIMMs of the plurality of DIMMs;
a storage controller to provide control operation for the storage of the data of the first set of DIMMs in the data storage device in a power loss condition for the computing system; and
a backup energy source to provide power to each of the first set of DIMMs, the data storage device, and the storage controller.

5. The computing system of claim 4 , wherein the backup energy source is a supercapacitor subsystem including one or more supercapacitors.

6. The computing system of claim 4 , wherein the data storage device is a solid state drive (SSD).

7. The computing system of claim 4 , wherein the storage controller includes a multiplexer to select one of the first set of DIMMs.

8. The computing system of claim 4 , wherein the plurality of DIMMs of the computing system includes the first set of DIMMs implemented as persistent memory and a second set of DIMMs implemented as volatile memory.

9. The computing system of claim 8 , wherein the storage controller to provide control operation for the storage of the data of the first set of DIMMs in the data storage device includes the storage controller to limit storage of data to a partial range of memory based on a setting.

10. A method comprising:
detecting a power loss in a computing system, the computing system including a plurality of dual in-line memory modules (DIMMs), wherein the plurality of DIMMs include at least a first set of DIMMs, each of the first set of DIMMs including:
a circuit board having a first side and a second side, the circuit board including a first set of electrical contacts on the first side and a second set of electrical contacts on the second side for connection with the computing system,
a connector installed in the circuit board of the DIMM, the connector including a connection to receive power from backup energy source, the connector being separate from the first set and second set of electrical contacts,
a plurality of volatile memory chips installed on the circuit board of the DIMM, wherein the plurality of volatile memory chips includes a first set of volatile memory chips installed in the first side of the circuit board and a second set of volatile memory chips installed in the second side of the circuit board, and
a controller installed in the circuit board of the DIMM, the controller to control back up of contents of the volatile memory chips in a power loss;

applying energy from a backup energy source to the plurality of DIMMs, to a storage controller, and to a data storage device; and
backing up data from each of the first set of DIMMs to the data storage device, wherein backing up the data includes the storage controller selecting the first set of DIMMs in a sequence for storage of data from each of the first set of DIMMs.

11. The method of claim 10 , further comprising restoring the data from the data storage device to each of the first set of DIMMs upon power up of the computing system.

12. The method of claim 10 , wherein backing up the data from each of the first set of DIMMs includes storing metadata regarding the data backup of each DIMM in the data storage device.

13. The method of claim 10 , wherein selecting the first set of DIMMs in a sequence includes selecting the first set of DIMMs according to a priority for each DIMM.

14. The method of claim 10 , further comprising removing the energy of the backup energy source from each of the first set of DIMMs upon completion of the backing up of data from each DIMM.

15. The method of claim 10 , wherein backing up data from each of plurality of the first set of DIMMs to the data storage device includes backing up a partial range of data from the first set of DIMMs based on a setting.

16. The DIMM of claim 1 , wherein the DIMM is to operate on power received from the backup energy source in the power loss condition.

17. The computing system of claim 4 , wherein the data storage device is operable to support address or data scrambling for data stored in the data storage device.

Assignees

• Intel Corp

Inventors

• Kumar Mohan J
• Nachimuthu Murugasamy K
• Vergis George

Classifications

• G06F2201/82

  Solving problems relating to consistency · CPC title

• G06F11/3034

  where the computing system component is a storage system, e.g. DASD based or network based (digital input from or digital output to record carriers G06F3/06; digital recording or reproducing G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097) · CPC title

• G06F3/0647

  Migration mechanisms · CPC title

• G06F11/3058

  Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations (thermal management in cooling arrangements of a computing system G06F1/206) · CPC title

• G06F11/00

  Error detection; Error correction; Monitoring (error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00) · CPC title