Backup of volatile memory to persistent storage

US9251047B1 · US · B1

Patent metadata
FieldValue
Publication numberUS-9251047-B1
Application numberUS-201313893153-A
CountryUS
Kind codeB1
Filing dateMay 13, 2013
Priority dateMay 13, 2013
Publication dateFeb 2, 2016
Grant dateFeb 2, 2016

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  1. Title

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  2. Abstract

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Approaches for automatically backing up data from volatile memory to persistent storage in the event of a power outage, blackout or other such failure are described. The approaches can be implemented on a computing device that includes a motherboard, central processing unit (CPU) a main power source, volatile memory (e.g., random access memory (RAM)), an alternate power source and circuitry (e.g., a specialized application-specific integrated circuit (ASIC)) for performing the backup of volatile memory to a persistent storage device. In the event of a power failure of the main power source, the alternate power source is configured to supply power to the specialized ASIC for backing up the data in the volatile memory. For example, when power failure is detected, the ASIC can read the data from the DIMM socket using power supplied from the alternate power source and write that data to a persistent storage device.

First claim

Opening claim text (preview).

What is claimed is: 1. A computing device, comprising: a main power source; and a motherboard configured to receive power from the main power source, the motherboard comprising: an application-specific integrated circuit (ASIC) configured to enable protection of data in an event of a power failure; a first socket configured to connect to a dual in-line memory module (DIMM); a second socket configured to connect to a persistent storage device; an alternate power source capable of supplying power to the ASIC, the first socket, the DIMM, the second socket and the persistent storage device; and a central processing unit (CPU) connected to the first socket, the CPU configured to read and write data to the DIMM over the first socket by utilizing the power supplied from the main power source; the application-specific integrated circuit (ASIC) coupled to the first socket and to the second socket, wherein in the event of a power failure on the main power source, the ASIC is configured to: disable protection of data on the ASIC at least until reboot has completed; initiate a pre-boot execution environment (PXE) of the computing device; access the data stored on the DIMM over the first socket using the power supplied by the alternate power source; encrypt the data by using an encryption key to generate encrypted data, the encryption key associated with a decryption key capable of being used to decrypt the data; write the encrypted data obtained over the first socket to the persistent storage device over the second socket by using the power supplied from the alternate power source; obtain the decryption key; decrypt the encrypted data stored in the persistent storage device using the decryption key to generate decrypted data; and load the decrypted data onto the DIMM while the computing device is in the pre-boot execution environment (PXE). 2. The computing device of claim 1 , wherein the alternate power source further comprises at least one of one or more capacitors, or a battery, and wherein the alternate power source is configured to: receive an indication of the power failure; and supply power to the ASIC, the first socket, the DIMM, the second socket, and the persistent storage device for backing up the data from the DIMM to the persistent storage device, wherein the persistent storage device is one of a NAND (Negated AND) flash drive or a SATA (Serial ATA) drive. 3. The computing device of claim 2 , wherein the persistent storage device is one of a NAND (Negated AND) flash drive or a SATA (Serial ATA) drive. 4. A device, comprising: a main power source; a motherboard including: a first socket configured to connect to a volatile memory, the volatile memory configured to receive power from the main power source, the volatile memory configured to store data; a second socket configured to connect to a persistent storage device; an alternate power source capable of supplying power to the first socket and to the second socket; and circuitry configured to, in the event of a power failure of the main power source, disable protection of data on the circuitry at least until reboot has completed; initiate a pre-boot execution environment (PXE) of the device; encrypt the data by using a cryptographic key to generate encrypted data, the cryptographic key associated with a decryption key used to decrypt the encrypted data; read the encrypted data from the first socket connected to the volatile memory; write the encrypted data to a second socket connected to the persistent storage device using power supplied by the alternate power source; decrypt the encrypted data stored in the persistent storage device using the cryptographic key to generate decrypted data; and load the decrypted data onto the DIMM while the device is in the pre-boot execution environment (PXE). 5. The device of claim 4 , wherein the data written to the persistent storage device is encrypted using the cryptographic key provisioned on at least one of: the circuitry or the persistent storage device. 6. The device of claim 5 , wherein the motherboard further includes: a central processing unit (CPU) operable to perform read and write operations to the volatile memory over the first socket, wherein upon rebooting the device after the power failure of the main power source, the CPU is configured to: retrieve the cryptographic key from at least one of: a secure store on the device or a remote computing device; and restore at least a portion of state on the volatile memory by writing the data stored in the persistent storage device to the volatile memory over the first socket. 7. The device of claim 4 , further comprising: an operating system loaded into memory of the device, the operating system configured to execute one or more applications, the operating system configured to provide an application programming interface (API) to enable the one or more applications to specify the data to be written to the persistent storage device in the event of the power failure of the main power source. 8. The device of claim 4 , wherein the first socket is connected to a dual in-line memory module (DIMM). 9. The device of claim 4 , wherein the circuitry is configured to write the data to the persistent storage device over the second socket comprising at least one of: a negated AND (NAND) socket, a serial ATA (SATA) connection, a peripheral component interconnect (PCI) connection, a universal serial bus (USB) connection, or a serial attached SCSI (SAS) connection. 10. The device of claim 4 , wherein the alternate power source further comprises at least one of: of one or more capacitors, or a battery. 11. A computer implemented method, comprising: detecting a power failure of a main power source on a motherboard of a computing device, the main power source configured to supply power to a first socket connected to a volatile memory of the computing device, the volatile memory configured to store data; in response to detecting the power failure, disabling protection of data on aspects of the motherboard at least until reboot has completed; initiating a pre-boot execution environment (PXE) of the computing device; encrypting the data by using a cryptographic key to generate encrypted data, the cryptographic key associated with a decryption key capable of being used to decrypt the encrypted data; reading the encrypted data from the first socket connected to the volatile memory by utilizing an alternate power source; writing the encrypted data obtained over the first socket connected to the volatile memory to a second socket on the motherboard, the second socket connected to a persistent storage device, the writing performed by utilizing the alternate power source that supplies power to at least the first socket and the second socket; decrypting the encrypted data stored in the persistent storage device using the decryption key to generate decrypted data; and loading the decrypted data onto the DIMM while the computing device is in the pre-boot execution environment (PXE). 12. The computer implemented method of claim 11 , wherein the writing the data to the second socket connected to the persistent storage device further comprises: encrypting the data on the persistent storage device using the cryptographic key obtained from at least one of: a trusted platform module (TPM) located on the computing device, or a remote computing device. 13. The computer implemented method of claim 12 , further comprising: rebooting the computing device after the power failure of the main power source; and restoring at least a portion of state in the volatile memory by writing

Assignees

Inventors

Classifications

  • Redundant power supplies (power supply failure G06F1/30) · CPC title

  • Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations (for resetting only G06F1/24) · CPC title

  • G06F12/00Primary

    Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06) · CPC title

  • in relation to content · CPC title

  • Providing cryptographic facilities or services · CPC title

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What does patent US9251047B1 cover?
Approaches for automatically backing up data from volatile memory to persistent storage in the event of a power outage, blackout or other such failure are described. The approaches can be implemented on a computing device that includes a motherboard, central processing unit (CPU) a main power source, volatile memory (e.g., random access memory (RAM)), an alternate power source and circuitry (e.…
Who is the assignee on this patent?
Amazon Tech Inc
What technology area does this patent fall under?
Primary CPC classification G06F12/00. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Feb 02 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).