System and method for a floating-point format for digital signal processors

Patent metadata

Field	Value
Publication number	US-9792087-B2
Application number	US-201213452701-A
Country	US
Kind code	B2
Filing date	Apr 20, 2012
Priority date	Apr 20, 2012
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

An embodiment of a system and method for performing a numerical operation on input data in a hybrid floating-point format includes representing input data as a sign bit, exponent bits, and mantissa bits. The exponent bits are represented as an unsigned integer including an exponent bias, and a signed numerical value of zero is represented as a first reserved combination of the mantissa bits and the exponent bits. Each of all other combinations of the mantissa bits and the exponent bits represents a real finite non-zero number. The mantissa bits are operated on with a “one” bit before a radix point for the all other combinations of the mantissa bits and the exponent bits.

First claim

What is claimed is:

1. An apparatus comprising:
a memory; and
a processor coupled to the memory, the processor configured to receive a multiple-input multiple output (MIMO) wireless baseband signal comprising input data having a sign bit, exponent bits, and mantissa bits, the processor comprising a hardware floating-point unit configured to perform a numerical operation on the input data in a 16-bit half-precision floating-point format,
wherein the exponent bits comprise an unsigned integer with an implied bias 16 providing symmetry in a 1/x reciprocal operation,
wherein a representation of a signed numerical value of zero comprises a first reserved combination of the mantissa bits and the exponent bits, wherein each of all other combinations of the mantissa bits and the exponent bits represents a real finite non-zero number,
wherein the mantissa bits are preceded by a bit “1” before a radix point for the all other combinations of the mantissa bits and the exponent bits; and
wherein the numerical operation comprises a multiplication or a division operation;

wherein the hardware floating-point unit comprises dedicated tail bit cut-off-only logic to cut off excess tail bits of an intermediate mantissa result without rounding the intermediate mantissa result;
wherein the hardware floating-point unit is further configured to produce from the numerical operation a result that is always either zero or a real finite non-zero number; and
wherein the processor is further configured to use the result of the numerical operation performed by the hardware floating-point unit in processing the MIMO wireless baseband signal.

2. The apparatus as in claim 1 , wherein the first reserved combination of the mantissa bits and the exponent bits comprises all the mantissa bits and all the exponent bits set to zero.

3. The apparatus as in claim 1 , wherein the apparatus is configured to set the mantissa bits and the exponent bits to a maximum finite value when the exponent bits produced by the numerical operation are computed to be greater than all the exponent bits set to one.

4. The apparatus as in claim 1 , wherein the apparatus is selectively configured in a first configuration to set the mantissa bits and the exponent bits to a second reserved combination of the mantissa bits and the exponent bits when an absolute value of the result produced by the numerical operation is less than a non-zero minimum absolute value among those represented by the all other combinations of the mantissa bits and the exponent bits, and in a second configuration to set the mantissa bits and the exponent bits to the non-zero minimum absolute value when the absolute value of the result produced by the numerical operation is less than the non-zero minimum absolute value.

5. The apparatus as in claim 4 , wherein the first configuration and the second configuration are selected by a flag.

6. The apparatus as in claim 4 , wherein the first reserved combination of the mantissa bits and the exponent bits and the second reserved combination of the mantissa bits and the exponent bits are equal.

7. The apparatus as in claim 1 , wherein the apparatus is configured to set all the mantissa bits and all the exponent bits to the first reserved combination of the mantissa bits and the exponent bits when the numerical operation produces all zeros for the exponent bits and a hidden bit “0” before the radix point.

8. The apparatus as in claim 1 , wherein the bit “1” before the radix point for the all other combinations of the mantissa bits and the exponent bits is hidden.

9. A method of performing a numerical operation on input data in a 16-bit half-precision floating-point format, the method comprising:
receiving a multiple-input multiple output (MIMO) wireless baseband signal comprising input data having a sign bit, exponent bits, and mantissa bits;
representing, by a hardware floating-point unit in accordance with the 16-bit half-precision floating-point format, the exponent bits as an unsigned integer with an implied bias 16 providing symmetry in a 1/x reciprocal operation;
representing, by the hardware floating-point unit, a signed numerical value of zero as a first reserved combination of the mantissa bits and the exponent bits, wherein each of all other combinations of the mantissa bits and the exponent bits represents a real finite non-zero number;
numerically operating, by the hardware floating-point unit, on the mantissa bits with a bit “1” before a radix point for the all other combinations of the mantissa bits and the exponent bits to produce a result, the numerical operation comprising a multiplication or a division operation;
cutting off excess tail bits of an intermediate mantissa result, without rounding the intermediate mantissa result, in the hardware floating-point unit with dedicated tail bit cut-off-only logic;
producing, by the hardware floating-point unit from the numerical operation, a result that is always either zero or a real finite non-zero number; and
using the result in processing the MIMO wireless baseband signal.

10. The method as recited in claim 9 , wherein the first reserved combination of the mantissa bits and the exponent bits comprises all the mantissa bits and all the exponent bits set to zero.

11. The method as recited in claim 9 , further comprising setting the mantissa bits and the exponent bits to a maximum finite value when the exponent bits produced by the numerical operation are computed to be greater than all the exponent bits set to one.

12. The method as recited in claim 9 , further comprising selectively setting in a first configuration the mantissa bits and the exponent bits to a second reserved combination of the mantissa bits and the exponent bits when an absolute value of the result is less than a non-zero minimum absolute value among those represented by the all other combinations of the mantissa bits and the exponent bits, and in a second configuration setting the mantissa bits and the exponent bits to the non-zero minimum absolute value when the absolute value of the result is less than the non-zero minimum absolute value.

13. The method as recited in claim 12 , wherein the first configuration and the second configuration are selected by a flag.

14. The method as recited in claim 12 , wherein the first reserved combination of the mantissa bits and the exponent bits and the second reserved combination of the mantissa bits and the exponent bits are equal.

15. The method as recited in claim 9 , further comprising setting all the mantissa bits and all the exponent bits to the first reserved combination of the mantissa bits and the exponent bits when the method produces all zeros for the exponent bits and a hidden bit “0” before the radix point.

16. The method as recited in claim 9 , wherein the bit “1” before the radix point for the all other combinations of the mantissa bits and the exponent bits is hidden.

17. An apparatus comprising:
a memory; and
a processor coupled to the memory, the processor configured to receive a wireless baseband signal comprising input data having a sign bit, exponent bits, and mantissa bits, the processor comprising a hardware floating-point unit configured to perform a numerical operation on the input data in a 28-bit full-precision floating-point format,
wherein the exponent bits comprise an unsigned integer including an exponent bias, and wherein the exponent bias is 64,
wherein a representation of a signed numerical value of zero comprises a first reserved combination of the mantissa bits and the exponent bits, wherein each of all other combi

Assignees

• Guo Yuanbin
• Sun Tong
• Chen Weizhong
• Futurewei Technologies Inc

Inventors

• Guo Yuanbin
• Sun Tong
• Chen Weizhong

Classifications

• G06F7/483 Primary

  Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)} · CPC title