CMOS compatible BioFET

Patent metadata

Field	Value
Publication number	US-9791406-B2
Application number	US-201615284283-A
Country	US
Kind code	B2
Filing date	Oct 3, 2016
Priority date	Oct 31, 2011
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity.

First claim

What is claimed is:

1. A method of providing a BioFET device; comprising:
providing a semiconductor substrate having a first surface and an opposing second surface;
forming a FET device on the semiconductor substrate, wherein the forming the FET device includes:
depositing a gate structure on the first surface of the semiconductor substrate and over a channel region of the FET device;

etching an opening in an isolation layer disposed on the second surface of the semiconductor substrate, wherein the opening exposes the channel region, the channel region including a portion of the second surface of the semiconductor substrate; and
forming an interface material on the exposed channel region in the opening.

2. The method of claim 1 , further comprising:
forming a source region and a drain region in the semiconductor substrate adjacent the gate structure, wherein the channel region interposes the source and drain regions.

3. The method of claim 2 , wherein the semiconductor substrate is a silicon-on-insulator (SOI) substrate.

4. The method of claim 3 , wherein the SOI substrate includes a first semiconductor layer and a second semiconductor layer interposed by the isolation layer, the method further comprising:
thinning the SOI substrate such that the first semiconductor layer is removed; and
thereafter etching the opening in the isolation layer to expose the second surface of the semiconductor substrate, wherein the second surface of the semiconductor substrate is disposed on the second semiconductor layer.

5. The method of claim 3 , wherein the SOI substrate includes a first semiconductor layer and a second semiconductor layer interposed by a buried insulating layer, the method further comprising:
thinning the semiconductor substrate to provide the second surface of the semiconductor substrate, wherein the thinning removes the first semiconductor layer and the buried insulating layer; and
depositing the isolation layer on the second surface of the semiconductor substrate is performed after the thinning.

6. The method of claim 1 , further comprising: forming a multi-layer interconnect (MLI) on the first surface of the semiconductor substrate.

7. The method of claim 6 , wherein the MLI is closer to the first surface of the semiconductor substrate than the second surface of the semiconductor substrate.

8. The method of claim 1 , further comprising:
forming a receptor on the interface material, wherein the receptor is selected from the group consisting of enzymes, antibodies, ligands, receptors, peptides, nucleotides, cells of organs, organisms and pieces of tissue.

9. The method of claim 8 , further comprising:
using the receptor to detect a target bio-molecule in a fluid disposed in a fluidic channel.

10. A method of forming a BioFET device, comprising:
providing a semiconductor substrate having a first surface and an opposing second surface;
forming a transistor over the first surface of the semiconductor substrate, wherein the transistor is nearer to the first surface of the semiconductor substrate than the second surface of the semiconductor substrate;
forming a multi-layer interconnect (MLI) coupled to the transistor and over the first surface of the semiconductor substrate, wherein the MLI is nearer to the first surface of the semiconductor substrate than the second surface of the semiconductor substrate;
thinning the semiconductor substrate by removing the second surface of the semiconductor substrate and exposing a channel region of the transistor in the semiconductor substrate;
etching an opening in the thinned semiconductor substrate extending to a conductive layer of the MLI;
depositing a conductive material in the opening; and
thereafter, forming an interface material on the exposed channel region of the transistor in the semiconductor substrate.

11. The method of claim 10 , wherein the MLI defines a dielectric top surface and wherein the thinning includes: attaching a carrier substrate to the dielectric top surface.

12. The method of claim 10 , wherein the depositing the conductive material in the opening includes depositing an aluminum copper alloy.

13. The method of claim 10 , further comprising:
after depositing the conductive material, forming a passivation layer over a first portion of the conductive material, wherein the passivation layer has an opening over a second portion of the conductive material.

14. The method of claim 10 , wherein the second portion of the conductive material forms an I/O pad for the BioFET device.

15. A method of fabricating a BioFET device, comprising:
providing a semiconductor substrate having a first surface and an opposing second surface;
forming a transistor device on the semiconductor substrate, wherein the forming the transistor device includes depositing a gate structure on the first surface of the semiconductor substrate and over a channel region of the transistor device;
forming a multi-layer interconnect (MLI) structure over the transistor device;
attaching a carrier substrate to a conductive layer of the MLI structure;
removing portions of the semiconductor substrate to expose the channel region while the carrier substrate is attached; and
forming an interface material on the exposed channel region.

16. The method of claim 15 , wherein the attaching the carrier substrate includes forming an interface between bonding elements on the carrier substrate and the conductive layer of the MLI structure.

17. The method of claim 16 , wherein the interface material is formed by one of a eutectic bond and a metal-to-metal diffusion bond.

18. The method of claim 15 , wherein the providing the semiconductor substrate includes providing a bulk silicon layer and an active layer, wherein an oxide layer interposes the bulk silicon layer and the active layer.

19. The method of claim 18 , wherein the removing the portions of the semiconductor substrate includes thinning the semiconductor substrate to remove the bulk silicon layer and expose the oxide layer.

20. The method of claim 19 , further comprising, after the thinning: etching an opening in the oxide layer to expose the channel region.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Kalnitsky Alexander
• Liu Yi-Shao
• Liang Kai-Chih
• Chu Chia-Hua
• Cheng Chun-Ren
• Cheng Chun-Wen

Classifications

• G01N27/4145 Primary

  specially adapted for biomolecules, e.g. gate electrode with immobilised receptors · CPC title

• G01N27/4148

  Integrated circuits therefor, e.g. fabricated by CMOS processing · CPC title

• G01N27/414

  Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS · CPC title

• H01L51/0093

  Electricity · mapped topic

• H01L21/84

  Electricity · mapped topic