Encapsulated semiconductor device package with heatsink opening, and methods of manufacture thereof

Patent metadata

Field	Value
Publication number	US-9787254-B2
Application number	US-201514862944-A
Country	US
Kind code	B2
Filing date	Sep 23, 2015
Priority date	Sep 23, 2015
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

Embodiments include packaged semiconductor devices and methods of manufacturing packaged semiconductor devices. A semiconductor die includes a conductive feature coupled to a bottom surface of the die. The conductive feature only partially covers the bottom die surface to define a conductor-less region that spans a portion of the bottom die surface. The die is encapsulated by attaching the encapsulant material to the bottom die surface (e.g., including over the conductor-less region). The encapsulant material includes an opening that exposes the conductive feature. After encapsulating the die, a heatsink is positioned within the opening, and a surface of the heatsink is attached to the conductive feature. Because the heatsink is attached after encapsulating the die, the heatsink sidewalls are not directly bonded to the encapsulant material.

First claim

What is claimed is:

1. A packaged semiconductor device comprising:
a semiconductor die having a top die surface and a bottom die surface;
a first conductive feature coupled to the bottom die surface, wherein the first conductive feature only partially covers the bottom die surface to define a first conductor-less region that spans a first portion of the bottom die surface;
encapsulant material over the first conductor-less region at the bottom die surface, wherein the encapsulant material includes a first opening that exposes the first conductive feature, and wherein the first opening has encapsulant sidewalls extending from an outer surface of the encapsulant material toward the bottom die surface; and
a heatsink having a first heatsink surface, a second heatsink surface, and heatsink sidewalls extending between the first and second heatsink surfaces, wherein the heatsink is positioned within the first opening in the encapsulant material, the first heatsink surface is attached to the first conductive feature, and the heatsink sidewalls are not directly bonded to the encapsulant material.

2. The device of claim 1 , wherein the heatsink is press-fit into the first opening so that the heatsink sidewalls are frictionally coupled with the encapsulant sidewalls.

3. The device of claim 1 , wherein a gap is present between the heatsink sidewalls and the encapsulant sidewalls.

4. The device of claim 3 , wherein an adhesive material is disposed within the gap.

5. The device of claim 1 , wherein a portion of the heatsink that is positioned within the first opening does not underlie the first conductor-less region.

6. The device of claim 1 , wherein the encapsulant material further includes a second opening that extends from a top surface of the encapsulant material toward the top die surface.

7. A packaged semiconductor device comprising:
a semiconductor die having
a top die surface,
a bottom die surface,
a transistor, and
a first filter circuit electrically coupled to the transistor, wherein the first filter circuit includes a first passive component formed in a portion of the semiconductor die, and wherein the first passive component is selected from an inductor and a capacitor,

a first conductive feature coupled to the bottom die surface, wherein the first conductive feature only partially covers the bottom die surface to define a first conductor-less region that spans a first portion of the bottom die surface, wherein a first current conducting terminal of the transistor is electrically coupled to the first conductive feature, and wherein the portion of the semiconductor die in which the first passive component is formed is directly opposite the first conductor-less region;
encapsulant material over the first conductor-less region at the bottom die surface, wherein the encapsulant material includes a first opening that exposes the first conductive feature, and wherein the first opening has encapsulant sidewalls extending from an outer surface of the encapsulant material toward the bottom die surface; and
a heatsink having a first heatsink surface, a second heatsink surface, and heatsink sidewalls extending between the first and second heatsink surfaces, wherein the heatsink is positioned within the first opening in the encapsulant material, the first heatsink surface is attached to the first conductive feature, and the heatsink sidewalls are not directly bonded to the encapsulant material.

8. The device of claim 7 , further comprising:
a second conductive feature coupled to the bottom die surface and physically separated from the first conductive feature across the first conductor-less region, wherein the second conductive feature is electrically coupled to the transistor; and
a first conductive lead coupled to the second conductive feature.

9. The device of claim 8 , further comprising:
a third conductive feature that is physically separated from the first conductive feature across a second conductor-less region spanning a second portion of the bottom die surface;
a second filter circuit electrically coupled to the transistor and to the third conductive feature, wherein the second filter circuit includes a second passive component formed in a portion of the semiconductor die that is directly opposite the second conductor-less region, and wherein the second passive component is selected from an inductor and a capacitor; and
a second conductive lead coupled to the third conductive feature.

10. The device of claim 9 , wherein the encapsulant material also is over the second conductor-less region at the bottom die surface, and the encapsulant material at least partially encapsulates the first and second conductive leads.

Assignees

• Freescale Semiconductor Inc
• Nxp Usa Inc

Inventors

• Abdo David F
• Jones Jeffrey K

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W72/07352

  changes in structures or sizes · CPC title

• H10W72/07336

  Soldering or alloying · CPC title

• H10W72/07331

  Connecting techniques · CPC title