Frequency jittering control circuit and the method thereof

Patent metadata

Field	Value
Publication number	US-9787196-B2
Application number	US-201615275165-A
Country	US
Kind code	B2
Filing date	Sep 23, 2016
Priority date	Sep 23, 2015
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

A control method of frequency jittering with a switching mode power supply, comprising: turning on and off a power switch of the switching mode power supply alternatively; updating a peak current signal of the switching mode power supply at a beginning of an on time of the power switch according to a length of a switching period before the beginning of the on time of the power switch, wherein the peak current signal varies as the length of the switching period changes.

First claim

What is claimed is:

1. A frequency jittering control circuit used with a switching mode power supply having a power switch, comprising:
a peak current signal generating circuit, having an input terminal configured to receive an on trigger signal having a pulse indicative of a beginning of an on time of the power switch, and an output terminal configured to provide a peak current signal based on the on trigger signal;
a peak comparator, having a first input terminal coupled to the output terminal of the peak current signal generating circuit to receive the peak current signal, a second input terminal configured to receive a current sense signal indicative of a current flowing through the power switch, and an output terminal configured to provide a current control signal based on the peak current signal and the current sense signal; and
a logic circuit, having a first input terminal configured to receive the on trigger signal, a second input terminal coupled to the output terminal of the peak comparator to receive the current control signal, and an output terminal configured to provide a power control signal based on the on trigger signal and the current control signal, wherein the power control signal controls on and off of the power switch; wherein
the peak current signal is updated at the beginning of the on time of the power switch, and a value of the peak current signal is determined by a length of a switching period before the beginning of the on time of the power switch.

2. The frequency jittering control circuit of claim 1 , wherein the value of the peak current signal has:
a first voltage value when the length of the switching period before the beginning of the on time of the power switch is shorter than a first preset value;
a second voltage value when the length of the switching period before the beginning of the on time of the power switch is longer than a second preset value; and
a third voltage value decreasing as increasing of the length of the switching period before the beginning of the on time of the power switch, when the length of the switching period is between the first preset value and the second preset value; wherein
the first preset value is smaller than the second preset value, and the first voltage value is larger than the second voltage value.

3. The frequency jittering control circuit of claim 1 , wherein the peak current signal generating circuit comprises:
a pulse width adjusting circuit, having an input terminal configured to receive the on trigger signal, and an output terminal configured to provide a pulse width signal based on the on trigger signal; and
a peak value control circuit, having an input terminal coupled to the output terminal of the pulse width adjusting circuit to receive the pulse width signal, and an output terminal configured to provide the peak current signal based on the pulse width signal.

4. The frequency jittering control circuit of claim 3 , wherein the pulse width signal has a pulse started from the pulse of the on trigger signal and ended after a preset time period.

5. The frequency jittering control circuit of claim 3 , wherein the peak value control circuit comprises:
a capacitor having a first terminal and a second terminal, wherein the second terminal is coupled to a ground reference;
a first voltage source, coupled in parallel to the capacitor by a sample switch, wherein a voltage across the capacitor is clamped to the first voltage value provided by the first voltage source when the sample switch is on;
a current source, coupled in parallel with the capacitor;
a second voltage source, coupled in parallel to the capacitor by a diode, wherein the voltage across the capacitor is clamped to the second voltage value provided by the second voltage source when the diode is on; and
a sample and hold circuit, having an input terminal coupled to the first terminal of the capacitor, and an output configured to provide the peak current signal; wherein
the sample and hold circuit samples and holds the voltage across the capacitor at the beginning of the on time of the power switch.

6. The frequency jittering control circuit of claim 1 , wherein the first voltage value and the second voltage value are constant.

7. The frequency jittering control circuit of claim 1 , wherein the first voltage value is varying, and the second voltage value is constant.

8. The frequency jittering control circuit of claim 1 , wherein the first voltage value and the second voltage value are both varying.

9. The frequency jittering control circuit of claim 1 , wherein the first voltage value is constant, and the second voltage value is varying.

10. A switching mode power supply, comprising:
a switching circuit having a power switch being turned on and off alternatively to convert an input voltage to an output voltage;
a frequency jittering control circuit configured to provide a power control signal to control the on and off of the power switch, wherein the frequency jittering control circuit comprises:
a peak current signal generating circuit having an input terminal configured to receive an on trigger signal having a pulse indicative of a beginning of an on time of the power switch, and an output terminal configured to provide a peak current signal based on the on trigger signal;
a peak comparator having a first input terminal coupled to the output terminal of the peak current signal generating circuit to receive the peak current signal, a second input terminal configured to receive a current sense signal indicative of a current flowing through the power switch, and an output terminal configured to provide a current control signal based on the peak current signal and the current sense signal; and
a logic circuit having a first input terminal configured to receive the on trigger signal, a second input terminal coupled to the output terminal of the peak comparator to receive the current control signal, and an output terminal configured to provide a power control signal based on the on trigger signal and the current control signal, wherein the power control signal controls on and off of the power switch;
wherein the peak current signal is updated at the beginning of the on time of the power switch, and a value of the peak current signal is determined by a length of a switching period before the beginning of the on time of the power switch.

11. The switching mode power supply of claim 10 , wherein the value of the peak current signal has:
a first voltage value when the length of the switching period before the beginning of the on time of the power switch is shorter than a first preset value;
a second voltage value when the length of the switching period before the beginning of the on time of the power switch is longer than a second preset value; and
a third voltage value decreasing as increasing of the length of the switching period before the beginning of the on time of the power switch, when the length of the switching period is between the first preset value and the second preset value;
wherein the first preset value is smaller than the second preset value, and the first voltage value is larger than the second voltage value.

12. The switching mode power supply of claim 10 , wherein the peak current signal generating circuit comprises:
a pulse width adjusting circuit having an input terminal configured to receive the on trigger signal, and an output terminal configured to provide a pulse width signal based on the on trigger signal; and
a peak value control circuit having an input terminal coupled to the output terminal of the pulse width adjusting circuit to receive the pulse width signal, and an output terminal configured

Assignees

• Monolithic Power Systems Inc

Inventors

• Wang Siran

Classifications

• H02M3/33507 Primary

  with automatic control of the output voltage or current, e.g. flyback converters (H02M3/33561, H02M3/33569 take precedence) · CPC title

• G11C27/024

  using a capacitive memory element (G11C27/04 takes precedence) · CPC title

• H02M1/44

  Circuits or arrangements for compensating for electromagnetic interference in converters or inverters · CPC title

• H02M1/08

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

• H02M2001/0009

  Electricity · mapped topic