Methods and systems for implementing adaptive FET drive voltage optimization for power stages of multi-phase voltage regulator circuits

Patent metadata

Field	Value
Publication number	US-9787172-B2
Application number	US-201414470455-A
Country	US
Kind code	B2
Filing date	Aug 27, 2014
Priority date	Jun 19, 2014
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

Methods and systems are disclosed that may be employed to implement adaptive FET drive voltage optimization for voltage regulator (VR) integrated power stages (IPstages) that have different MOSFET RDS(on) characteristics to improve VR efficiency and current-sense accuracy.

First claim

What is claimed is:

1. A system, comprising:
at least one integrated power stage (IPstage) comprising a voltage input, a voltage output, one or more field effect transistor (FET) switching devices coupled between the voltage input and the voltage output to provide regulated power to the voltage output, and an IPstage identification (ID) recognition module having a power device identification signal output that is indicative of an identity of the at least one IPstage;
at least one processing device coupled to control operation of the at least one IPstage, the at least one, processing device also being coupled to receive the power device identification signal output from the at least one IPstage;
a power stage gate drive voltage regulator (VR) coupled between the at least one processing device and the at least one IPstage, the power stage gate drive VR being configured to provide a regulated gate drive voltage to drive the FET switching devices of the at least one IPstage;
where the at least one processing device is configured to:
receive the power device identification signal output from the at least one IPstage,
determine a FET drive voltage control signal value based at least in part on the received power device identification signal, and
provide the FET drive voltage control signal to control the power stage gate drive VR to provide a determined FET drive voltage to drive the FET switching devices of the at least one IPstage while controlling the at least one IPstage to provide power to the voltage output;

where the at least one processing device coupled to control operation of the at least one IPstage is configured as a VR system controller;
where the system further comprises memory accessible by the VR system controller having information indicative of a FET drive voltage control signal value that corresponds to the identified IPstage stored thereon together with information indicative of FET drive voltage control signal values for different types of IPstages;
where the VR system controller is also coupled to receive the power device identification signal output from the at least one IPstage with the power stage gate drive VR being coupled between the VR system controller and the at least one IPstage; where the memory comprises external non-volatile memory (NVM) coupled to the VR system controller, the NVM storing information indicative of FET drive voltage control signal values corresponding to multiple different types of IPstages that include the at least one IPstage; and
where the VR controller is further configured to:
receive the power device identification signal output from the at least one IPstage,
determine the identity of the at least one IPstage based on the received power device identification signal,
retrieve information indicative of a FET drive voltage control signal value that corresponds to the identified IPstage from the NVM, and
provide the indicated FET drive voltage control signal value to the power stage gate drive VR; and

where the power stage gate drive VR is configured to provide a regulated gate drive voltage based on the value of the retrieved FET drive voltage control signal provided by the VR controller to drive a gate of the FET switching devices of the at least one IPstage while the VR controller controls the at least one IPstage to provide power to the voltage output.

2. A system, comprising:
at least one integrated power stage (IPstage) comprising a voltage input, a voltage output, one or more field effect transistor (FET) switching devices coupled between the voltage input and the voltage output to provide regulated power to the voltage output, and an IPstage identification (ID) recognition module having a power device identification signal output that is indicative of an identity of the at least one IPstage;
at least one processing device coupled to control operation of the at least one IPstage, the at least one processing device also being coupled to receive the power device identification signal output from the at least one IPstage;
a power stage gate drive voltage regulator (VR) coupled between the at least one processing device and the at least one IPstage, the power stage gate drive VR being configured to provide a regulated gate drive voltage to drive the FET switching devices of the at least one IPstage;
where the at least one processing device is configured to:
receive the power device identification signal output from the at least one IPstage;
determine a FET drive voltage control signal value based at least in part on the received power device identification signal, and
provide the FET drive voltage control signal to control the power stage gate drive VR to provide a determined FET drive voltage to drive the FET switching devices of the at least one IPstage while controlling the at least one IP stage to provide power to the voltage output;

where the at least one processing device coupled to control operation of the at least one IPstage is configured as a VR system controller;
where the system further comprises memory accessible by the VR system controller having information indicative of a FET drive voltage control signal value that corresponds to the identified IPstage stored thereon together with information indicative of FET drive voltage control signal values for different types of IP stages;
where the VR system controller is also coupled to receive the power device identification signal output from the at least one IPstage with the power stage gate drive VR being coupled between the VR system controller and the at least one IPstage; where the memory comprises an internal memory register of the VR system controller that stores information indicative of FET drive voltage control signal values corresponding to multiple different types of IPstages that include the at least one IPstage; and
where the VR controller is further configured to:
receive the power device identification signal output from the at least one IPstage,
determine the identity of the at least one IPstage based on the received power device identification signal,
retrieve information indicative of a FET drive voltage control signal value that corresponds to the identified IPstage from the internal memory register, and
provide the indicated FET drive voltage control signal value to the power stage gate drive VR; and

where the power stage gate drive VR is configured to provide a regulated gate drive voltage based on the value of the retrieved FET drive voltage control signal provided by the VR controller to drive the gate of the FET switching devices of the at least one IPstage while the VR controller controls the at least one IPstage to provide power to the VR system voltage output.

3. The system of claim 2 , where the FET switching devices comprise MOSFET switching devices.

4. A system, comprising:
at least one integrated power stage (IPstage) comprising a voltage input, a voltage output, one or more field effect transistor (FET) switching devices coupled between the voltage input and the voltage output to provide regulated power to the voltage output, and an IPstage identification (ID) recognition module having a power device identification signal output that is indicative of an identity of the at least one IPstage;
at least one processing device coupled to control operation of the at least one IPstage, the at least one processing device also being coupled to receive the power device identification signal output from the at least one IPstage;
a power stage gate drive voltage regulator (VR) coupled between the at least one processing device and the at least one IPstage, the power stage gate drive VR being configured to provide a regulated gate drive voltage to drive the FET switching devices of the at least one IPstage;
where the at least one processing device is configured to:
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Assignees

• Luo Shiguo
• Johnson Ralph H
• Dell Products Lp

Inventors

• Luo Shiguo
• Johnson Ralph H

Classifications

• H02M3/157 Primary

  with digital control · CPC title

• H02M3/1584

  with a plurality of power processing stages connected in parallel · CPC title

• G06F1/26

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• H02M1/084 Primary

  using a control circuit common to several phases of a multi-phase system · CPC title

• H02M1/08

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title