Methods and systems for improving light load efficiency for power stages of multi-phase voltage regulator circuits

Patent metadata

Field	Value
Publication number	US-9647543-B2
Application number	US-201514963903-A
Country	US
Kind code	B2
Filing date	Dec 9, 2015
Priority date	Jun 19, 2014
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

Methods and systems are disclosed that may be employed to improve efficiency of smart integrated power stages (IPstages) of multi-phase VR systems while operating under relatively light, ultra-light, or partial or reduced loads. The disclosed methods and systems may be implemented to improve VR system light load efficiency by providing and enabling reduced power IPstage operating modes in one or more smart IPstage/s of a VR system, and by enabling state transition between IPstage active and reduced power operating modes such as IPstage standby and IPstage hibernation modes.

First claim

What is claimed is:

1. A system, comprising:
at least one integrated power stage (IPstage) comprising an IPstage processing device, power-consuming circuitry, and a power output;
where the power output of the IPstage is configured to be coupled to a bootstrap capacitor;
where the IPstage is configured to be coupled to receive signals from a separate processing device configured as a voltage regulator (VR) controller that command the IPstage to selectively provide or not provide power to the power output of the IPstage; and
where the IPstage processing device is configured to:
monitor voltage on the bootstrap capacitor while the IPstage is commanded by the VR controller to not provide power to the power output of the IP stage,
control at least a portion of the power-consuming circuitry of the IPstage to supply current to the bootstrap capacitor to increase voltage on the bootstrap capacitor when the monitored voltage of the bootstrap capacitor becomes less than or equal to a pre-determined refresh voltage (V bootMin ) threshold value while the IPstage processing device is not providing power to the power output of the IPstage, and
receive a hibernation activation signal from the VR controller; and where the IPstage processing device is configured to respond to the hibernation activation signal and enter an IPstage hibernation mode by turning off the at least a portion of the power-consuming circuitry of the IPstage such that the bootstrap capacitor is not refreshed during the duration of the IPstage hibernation mode.

2. The system of claim 1 , where the power-consuming circuitry of the IPstage comprises at least one of current sense circuitry configured to sense output current from the IPstage power output, half-bridge power circuitry configured to provide output power to the IPstage power output, gate driver circuitry configured to drive the half-bridge power circuitry, or a combination thereof.

3. The system of claim 1 , where the IPstage processing device is configured to perform the following steps when not in the IPstage hibernation mode and while the IPstage processing device is not providing power to the power output of the IPstage:
control the at least a portion of the power-consuming circuitry of the IPstage to supply current to the bootstrap capacitor to increase voltage on the bootstrap capacitor when the monitored voltage of the bootstrap capacitor becomes less than or equal to a pre-determined refresh voltage (V bootMin ) threshold value while the IPstage processing device is not providing power to the power output of the IPstage; and
then control the at least a portion of the power-consuming circuitry of the IPstage to stop supplying current to the bootstrap capacitor when the monitored voltage of the bootstrap capacitor increases to greater than or equal to a pre-determined maximum Vboot Refresh (V bootMax ) threshold value while the IPstage processing device is not providing power to the power output of the IPstage.

4. The system of claim 1 , where the IPstage is further configured to receive a hibernation deactivation signal from the VR controller controller; and where the IPstage processing device is configured to respond to the hibernation deactivation signal and exit the IPstage hibernation mode to an active power regulation mode by turning on the at least a portion of the power-consuming circuitry of the IPstage.

5. The system of claim 4 , where the IPstage is configured to be coupled to the VR controller by a bi-directional power device identification signal path that is configured to communicate signals between the IPstage and the VR controller that are indicative of the identity of the IPstage; and where the IPstage is further configured to recognize a first signal on the power device identification signal path from the VR controller controller as the hibernation activation signal; and to recognize a second signal on the power device identification signal path from the VR controller controller as the hibernation deactivation signal.

6. The system of claim 1 , where the at least a portion of the power-consuming circuitry of the IPstage of the IPstage comprises at least a portion of half-bridge power circuitry configured to provide output power to the IPstage power output; and where the IPstage processing device is configured to control the at least a portion of the half-bridge power circuitry of the IPstage to supply current to the bootstrap capacitor to increase voltage on the bootstrap capacitor when the monitored voltage of the bootstrap capacitor becomes less than or equal to the pre-determined refresh voltage (V bootMin ) threshold value while the IPstage processing device is not providing power to the power output of the IPstage.

7. A method of operating a voltage regulator (VR) system that includes at least one processing device, comprising:
using the at least one processing device as a voltage regulator (VR) controller to control operation of at least one integrated power stage (IPstage) of the VR system, the IPstage having a separate IPstage processing device, power-consuming circuitry, and a power output that is coupled to a bootstrap capacitor;
using the VR controller to provide signals to the IPstage to command the IPstage to selectively provide or not provide power to the power output of the IPstage; and
using the IPstage processing device to:
monitor voltage on the bootstrap capacitor while the IPstage is commanded by the VR controller to not provide power to the power output of the IP stage, and
control at least a portion of the power-consuming circuitry of the IPstage to supply current to the bootstrap capacitor to increase voltage on the bootstrap capacitor when the monitored voltage of the bootstrap capacitor becomes less than or equal to a pre-determined refresh voltage (V bootMin ) threshold value while the IPstage processing device is not providing power to the power output of the IPstage; and

where the method further comprises:
providing a hibernation activation signal from the VR controller to the IPstage, and
using the IPstage processing device to respond to the hibernation activation signal and enter an IPstage hibernation mode by turning off the at least a portion of the power-consuming circuitry of the IPstage such that the bootstrap capacitor is not refreshed during the duration of the IPstage hibernation mode.

8. The method of claim 7 , where the power-consuming circuitry of the IPstage comprises at least one of current sense circuitry configured to sense output current from the IPstage power output, half-bridge power circuitry configured to provide output power to the IPstage power output, gate driver circuitry configured to drive the half-bridge power circuitry, or a combination thereof.

9. The method of claim 7 , further comprising using the IPstage processing device to perform the following steps when not in the IPstage hibernation mode and while the IPstage processing device is not providing power to the power output of the IPstage:
control the at least a portion of the power-consuming circuitry of the IPstage to supply current to the bootstrap capacitor to increase voltage on the bootstrap capacitor when the monitored voltage of the bootstrap capacitor becomes less than or equal to a pre-determined refresh voltage (V bootMin ) threshold value while the IPstage processing device is not providing power to the power output of the IPstage; and
then control the at least a portion of the power-consuming circuitry of the IPstage to stop supplying current to the bootstrap capacitor when the monitored voltage of the bootstrap capacitor increases to greater than or equal to a pre-determined maximum Vboot Refresh (V bootMax ) threshold value while the IPstage processing device is not

Assignees

• Luo Shiguo
• Zhang Kejiu
• Li Hang
• Dell Products Lp

Inventors

• Luo Shiguo
• Zhang Kejiu
• Li Hang

Classifications

• G06F1/26 Primary

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• Y02B70/1466

  Cross-Sectional Technologies · mapped topic

• H02M2001/0006

  Electricity · mapped topic

• H02M3/157 Primary

  with digital control · CPC title

• G06F1/32

  Means for saving power · CPC title