Pocketed circuit board

Patent metadata

Field	Value
Publication number	US-9786977-B2
Application number	US-201514965510-A
Country	US
Kind code	B2
Filing date	Dec 10, 2015
Priority date	Dec 10, 2015
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

An example circuit board structure includes: a substrate; and vias that are electrically conductive and that pass through the substrate to enable electrical connection through the circuit board structure. The substrate is thinner, and lengths of the vias are shorter, in first areas of the circuit board structure that deliver first speed signals than in second areas of the circuit board structure that deliver second speed signals and power. The first speed signals have a shorter rise time than the second speed signals.

First claim

What is claimed is:

1. A circuit board structure comprising:
a substrate; and
vias that are electrically conductive and that pass through the substrate to enable electrical connection through the circuit board structure;
wherein the substrate is thinner in first areas of the circuit board structure that deliver first type signals than in second areas of the circuit board structure that deliver second type signals.

2. The circuit board structure of claim 1 , wherein lengths of the vias are shorter in the first areas of the substrate; and
wherein the first type signals comprise first speed signals, the second type signals comprise second speed signals and power, and the first speed signals have a shorter rise time than the second speed signals.

3. The circuit board structure of claim 1 , wherein the substrate comprises one or more pockets that are at thinner parts of the substrate in the first areas.

4. The circuit board structure of claim 3 , wherein the substrate comprises multiple layers, the one or more pockets being formed by removal of at least some of the multiple layers.

5. The circuit board structure of claim 1 , further comprising:
a backing plate disposed adjacent to thinner parts of the substrate in the first areas to reinforce the substrate.

6. The circuit board structure of claim 2 , further comprising:
an interposer adjacent to the substrate and comprising electrical paths that connect to the vias to establish a signal path, the interposer comprising contacts for mating to an external device, the interposer comprising a structure that provides a micro-compliant electrical path from the circuit board structure to an assembly that carries the first speed signals to/from a source/receiver.

7. The circuit board structure of claim 1 , further comprising:
one or more alignment pins through the substrate for aligning to one or more connectors to the circuit board structure.

8. The circuit board structure of claim 2 , wherein the first speed signals have speeds that meet or exceed 16 gigabits-per-second, and the second speed signals have speeds that are less than 16 gigabits-per-second; or
wherein the first speed signals have speeds that meet or exceed 16 gigahertz, and the second speed signals have speeds that are less than 16 gigahertz.

9. The circuit board structure of claim 2 , wherein the first speed signals have speeds that meet or exceed 32 gigabits-per-second, and the second speed signals have speeds that are less than 32 gigabits-per-second; or
wherein the first speed signals have speeds that meet or exceed 32 gigahertz, and the second speed signals have speeds that are less than 32 gigahertz.

10. The circuit board structure of claim 2 , wherein the first speed signals have speeds that meet or exceed 64 gigabits-per-second, and the second speed signals have speeds that are less than 64 gigabits-per-second; or
wherein the first speed signals have speeds that meet or exceed 64 gigahertz, and the second speed signals have speeds that are less than 64 gigahertz.

11. The circuit board structure of claim 1 , wherein thinner parts of the substrate in the first areas have a thickness that is 20% or less of thicker parts of the substrate in the second areas.

12. The circuit board structure of claim 1 , wherein thinner parts of the substrate in the first areas have a thickness that is 30% or less of thicker parts of the substrate in the second areas.

13. The circuit board structure of claim 1 , wherein thinner parts of the substrate in the first areas have a thickness that is 40% or less of thicker parts of the substrate in the second areas.

14. The circuit board structure of claim 1 , further comprising a tower that mates to a complementary pocket in another circuit board.

15. A device interface board for connection between a device under test and test equipment, the device interface board comprising the circuit board structure of claim 1 .

16. The circuit board structure of claim 1 , wherein the first type signals comprise radio frequency (RF) signals and the second type signals comprise non-RF signals.

17. The circuit board structure of claim 1 , wherein the first areas of the substrate comprise an area that includes a first dielectric having metal on which a microwave component is mountable, the first dielectric being adjacent to a microwave dielectric layer.

18. The circuit board structure of claim 1 , wherein the second areas of the substrate comprise an area that includes a stack of dielectric layers that that do not include a microwave dielectric.

19. The circuit board structure of claim 1 , wherein the vias have a diameter that is based on a thickness of the first areas of the substrate.

20. The circuit board structure of claim 1 , wherein the vias in the first areas of the substrate have diameters that are less than diameters of vias in the second areas of the substrate.

21. A device interface board (DIB) comprising:
a substrate having a first area of a first thickness and a second area of a second thickness, the second thickness being greater than the first thickness; and
vias that are electrically conductive and that pass through the first area to enable electrical connection between the vias and a device under test, where vias that pass through the first area are reserved for transmission of signals having at least a minimum speed.

22. The DIB of claim 21 , wherein the DIB comprises vias through the second area that are reserved for transmission of signals that do not meet the minimum speed.

23. The DIB of claim 21 , further comprising:
a backing plate disposed adjacent to the first areas to reinforce the substrate.

24. The DIB of claim 21 , further comprising:
one or more alignment pins through the substrate for aligning to one or more connectors that are connectable to the DIB.

25. The DIB of claim 21 , wherein the minimum speed is 16 gigabits-per-second, 32 gigabits-per-second, or 64 gigabits-per-second; or
wherein the minimum speed is 16 gigahertz, 32 gigahertz, or 64 gigahertz.

26. The DIB of claim 21 , wherein the first areas of the substrate have a thickness that is 20% or less of the second areas of the substrate.

Assignees

• Teradyne Inc

Inventors

• Lyons Timothy Daniel
• Parrish Frank B
• Sinsheimer Roger Allen
• Donovan Brian G
• Vayner Vladimir
• Creager Brandon E
• Wadell Brian C

Classifications

• H05K1/115 Primary

  Via connections; Lands around holes or via connections (H05K1/112 takes precedence) · CPC title

• H05K1/024

  Dielectric details, e.g. changing the dielectric material around a transmission line · CPC title

• H05K2201/09036

  Recesses or grooves in insulating substrate · CPC title

• H05K1/0243

  Printed circuits associated with mounted high frequency components · CPC title

• H01P3/082 Primary

  Multilayer dielectric · CPC title